Added basic test

.github/workflows/main.yml

@@ -41,3 +41,6 @@ jobs:
 
       - name: Compile
         run: make compile
+
+      - name: Unit test
+        run: make test

.gitignore

@@ -2,4 +2,5 @@
 out/
 .idea/
 .idea_modules/
+test_run_dir/
 

src/main/scala/CacheParameters.scala

@@ -15,6 +15,7 @@ case class CacheParameters(
   sets:         Int = 1024,
   blockBytes:   Int = 64,
   replacement:  String = "plru",
+  mshrs: Int = 16,
   channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(32),
   echoField:    Seq[BundleFieldBase] = Nil,
   reqField:     Seq[BundleFieldBase] = Nil, // master
@@ -23,5 +24,5 @@ case class CacheParameters(
   respField:    Seq[BundleFieldBase] = Nil) {
   require(ways > 0)
   require(sets > 0)
-  require(channelBytes.d.get >= 64)
+  require(channelBytes.d.get >= 8)
 }

src/main/scala/HuanCun.scala

@@ -11,13 +11,14 @@ trait HasHuanCunParameters {
   val cacheParams = p(CacheParamsKey)
   val blockBytes = cacheParams.blockBytes
 
+  val mshrs = cacheParams.mshrs
   val blocks = cacheParams.ways * cacheParams.sets
   val sizeBytes = blocks * blockBytes
 }
 
-abstract class HuanCunModule(implicit p: Parameters) extends LazyModule with HasHuanCunParameters
+abstract class HuanCunModule(implicit p: Parameters) extends Module with HasHuanCunParameters
 
-class HuanCun(implicit p: Parameters) extends HuanCunModule {
+class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParameters {
 
   val xfer = TransferSizes(blockBytes, blockBytes)
   val atom = TransferSizes(1, cacheParams.channelBytes.d.get)
@@ -31,7 +32,8 @@ class HuanCun(implicit p: Parameters) extends HuanCunModule {
             name = cacheParams.name,
             supports = TLSlaveToMasterTransferSizes(
               probe = xfer
-            )
+            ),
+            sourceId = IdRange(0, cacheParams.mshrs),
           )
         ),
         channelBytes = cacheParams.channelBytes,
@@ -62,7 +64,8 @@ class HuanCun(implicit p: Parameters) extends HuanCunModule {
         beatBytes = 32,
         minLatency = 2,
         responseFields = cacheParams.respField,
-        requestKeys = cacheParams.reqKey
+        requestKeys = cacheParams.reqKey,
+        endSinkId = cacheParams.mshrs + 2
       )
     }
   )
@@ -73,7 +76,12 @@ class HuanCun(implicit p: Parameters) extends HuanCunModule {
 
     node.in.zip(node.out).foreach {
       case ((in, edgeIn), (out, edgeOut)) =>
-        in <> out
+        out <> in
+        val header = s"======== HuanCun: ${cacheParams.name} ========"
+        println(header)
+        println("clients: " + edgeIn.client.clients.map(_.name).mkString(" "))
+        println("managers: " + edgeOut.manager.managers.map(_.name).mkString(" "))
+        println(header.map(_ => "=").mkString(""))
     }
 
   }

src/test/scala/BasicTester.scala

@@ -0,0 +1,37 @@
+package HuanCun
+
+import org.scalatest._
+import chiseltest._
+import chisel3._
+import chiseltest.experimental.TestOptionBuilder.ChiselScalatestOptionBuilder
+import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, LazyModuleImpLike}
+import freechips.rocketchip.tilelink.{TLCacheCork, TLFuzzer, TLIdentityNode, TLRAM}
+
+class BasicTester extends L2Tester {
+
+  class TestTop extends LazyModule {
+    val cache = LazyModule(new HuanCun())
+    val fuzzer = LazyModule(new TLFuzzer(
+      nOperations = 2 * cache.cacheParams.mshrs, inFlight = cache.cacheParams.mshrs
+    ))
+    val ram = LazyModule(new TLRAM(AddressSet(0, 0xffff)))
+
+    ram.node := TLCacheCork() := cache.node := fuzzer.node
+    lazy val module = new LazyModuleImp(this){
+      val pass = IO(Output(Bool()))
+      pass := fuzzer.module.io.finished
+    }
+  }
+
+  it should "read and write TLRAM correctly" in {
+
+    val top = LazyModule(new TestTop)
+
+    test(top.module).withAnnotations(testAnnos) { dut =>
+      while(!dut.pass.peek().litToBoolean){
+        dut.clock.step(1)
+      }
+    }
+  }
+
+}

src/test/scala/L2Tester.scala

@@ -1,9 +1,20 @@
 package HuanCun
 
+import chipsalliance.rocketchip.config.Config
 import chiseltest._
+import chiseltest.internal.VerilatorBackendAnnotation
+import firrtl.AnnotationSeq
 import org.scalatest.flatspec._
 import org.scalatest.matchers.should._
 
 abstract class L2Tester extends AnyFlatSpec with ChiselScalatestTester with Matchers {
   behavior of "L2"
+  implicit val defaultConfig = new Config((_, _, _) => {
+    case CacheParamsKey => CacheParameters()
+  })
+  var testAnnos: AnnotationSeq = Seq()
 }
+
+trait WithVerilatorBackend { this: L2Tester =>
+  testAnnos = testAnnos :+ VerilatorBackendAnnotation
+}