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[Intel] Provides the overclocking bins with unlocked processors
1 parent dbc0e1e commit db15a83

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9 files changed

+212
-7
lines changed

9 files changed

+212
-7
lines changed

‎x86_64/corefreq-cli-json.c‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1400,9 +1400,20 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
14001400
}
14011401
json_end_object(&s);
14021402
}
1403-
json_key(&s, "FactoryFreq");
1404-
json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Freq);
1403+
json_key(&s, "Factory");
1404+
{
1405+
json_start_object(&s);
1406+
json_key(&s, "Freq");
1407+
json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Freq);
1408+
json_key(&s, "Ratio");
1409+
json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Ratio);
1410+
json_key(&s, "Bins");
1411+
json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Bins);
1412+
json_key(&s, "Overclock");
1413+
json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Overclock);
14051414

1415+
json_end_object(&s);
1416+
}
14061417
json_key(&s, "InvariantTSC");
14071418
json_literal(&s, "%u", RO(Shm)->Proc.Features.InvariantTSC);
14081419
json_key(&s, "HyperThreading");
@@ -1449,6 +1460,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
14491460
json_literal(&s, "%u", RO(Shm)->Proc.Features.SpecTurboRatio);
14501461
json_key(&s, "XtraCOF");
14511462
json_literal(&s, "%u", RO(Shm)->Proc.Features.XtraCOF);
1463+
json_key(&s, "OC_Enable");
1464+
json_literal(&s, "%u", RO(Shm)->Proc.Features.OC_Enable);
1465+
json_key(&s, "OC_Lock");
1466+
json_literal(&s, "%u", RO(Shm)->Proc.Features.OC_Lock);
14521467

14531468
json_end_object(&s);
14541469
}

‎x86_64/corefreq-cli-rsc-en.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -854,6 +854,7 @@
854854
#define RSC_FREQUENCY_CODE_EN "Frequency"
855855
#define RSC_RATIO_CODE_EN "Ratio"
856856
#define RSC_FACTORY_CODE_EN "Factory"
857+
#define RSC_OVERCLOCK_CODE_EN "Overclock"
857858
#define RSC_PERFORMANCE_CODE_EN "Performance"
858859
#define RSC_TARGET_CODE_EN "Target"
859860
#define RSC_LEVEL_CODE_EN "Level"
@@ -1246,6 +1247,7 @@
12461247
#define RSC_TECHNOLOGIES_HDCP_CODE_EN "Digital Content Protection"
12471248
#define RSC_TECHNOLOGIES_IPU_CODE_EN "Image Processing Unit"
12481249
#define RSC_TECHNOLOGIES_VPU_CODE_EN "Vision Processing Unit"
1250+
#define RSC_TECHNOLOGIES_OC_CODE_EN "Overclocking"
12491251

12501252
#define RSC_TECH_AMD_CPB_COMM_CODE_EN " Hardware Configuration::CpbDis "
12511253
#define RSC_TECH_INTEL_EEO_COMM_CODE_EN " Skylake::Power Control::EEO_Disable "
@@ -2338,6 +2340,7 @@
23382340
#define RSC_CPPC_CODE "CPPC"
23392341
#define RSC_MAX_CODE "Max"
23402342
#define RSC_MIN_CODE "Min"
2343+
#define RSC_BIN_CODE "Bin"
23412344
#define RSC_UCLK_CODE "CLK"
23422345
#define RSC_MCLK_CODE "MEM"
23432346
#define RSC_TGT_CODE "TGT"

‎x86_64/corefreq-cli-rsc-fr.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
357357
#define RSC_FREQUENCY_CODE_FR "Fr""\xa9""quence"
358358
#define RSC_RATIO_CODE_FR "Ratio"
359359
#define RSC_FACTORY_CODE_FR "Usine"
360+
#define RSC_OVERCLOCK_CODE_FR "Overclock"
360361
#define RSC_PERFORMANCE_CODE_FR "Performance"
361362
#define RSC_TARGET_CODE_FR "Cible"
362363
#define RSC_LEVEL_CODE_FR "Niveau"
@@ -726,6 +727,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
726727

727728
#define RSC_TECHNOLOGIES_IPU_CODE_FR "Unit""\xa9"" de traitement d'images"
728729
#define RSC_TECHNOLOGIES_VPU_CODE_FR "Unit""\xa9"" de traitement visuel"
730+
#define RSC_TECHNOLOGIES_OC_CODE_FR "Surcaden""\xa7""age"
729731

730732
#define RSC_TECH_AMD_CPB_COMM_CODE_FR RSC_TECH_AMD_CPB_COMM_CODE_EN
731733
#define RSC_TECH_INTEL_EEO_COMM_CODE_FR RSC_TECH_INTEL_EEO_COMM_CODE_EN

‎x86_64/corefreq-cli-rsc.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -553,6 +553,7 @@ RESOURCE_ST Resource[] = {
553553
LDT(RSC_FREQUENCY),
554554
LDT(RSC_RATIO),
555555
LDT(RSC_FACTORY),
556+
LDT(RSC_OVERCLOCK),
556557
LDT(RSC_PERFORMANCE),
557558
LDT(RSC_TARGET),
558559
LDT(RSC_LEVEL),
@@ -581,6 +582,7 @@ RESOURCE_ST Resource[] = {
581582
LDQ(RSC_CPPC),
582583
LDQ(RSC_MAX),
583584
LDQ(RSC_MIN),
585+
LDQ(RSC_BIN),
584586
LDQ(RSC_UCLK),
585587
LDQ(RSC_MCLK),
586588
LDQ(RSC_TGT),
@@ -1157,6 +1159,7 @@ RESOURCE_ST Resource[] = {
11571159
LDT(RSC_TECH_HDCP_COMM),
11581160
LDT(RSC_TECHNOLOGIES_IPU),
11591161
LDT(RSC_TECHNOLOGIES_VPU),
1162+
LDT(RSC_TECHNOLOGIES_OC),
11601163
LDT(RSC_PERF_MON_TITLE),
11611164
LDT(RSC_PERF_CAPS_TITLE),
11621165
LDT(RSC_VERSION),

‎x86_64/corefreq-cli-rsc.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -356,6 +356,7 @@ enum {
356356
RSC_FREQUENCY,
357357
RSC_RATIO,
358358
RSC_FACTORY,
359+
RSC_OVERCLOCK,
359360
RSC_PERFORMANCE,
360361
RSC_TARGET,
361362
RSC_LEVEL,
@@ -384,6 +385,7 @@ enum {
384385
RSC_CPPC,
385386
RSC_MAX,
386387
RSC_MIN,
388+
RSC_BIN,
387389
RSC_UCLK,
388390
RSC_MCLK,
389391
RSC_TGT,
@@ -960,6 +962,7 @@ enum {
960962
RSC_TECH_HDCP_COMM,
961963
RSC_TECHNOLOGIES_IPU,
962964
RSC_TECHNOLOGIES_VPU,
965+
RSC_TECHNOLOGIES_OC,
963966
RSC_PERF_MON_TITLE,
964967
RSC_PERF_CAPS_TITLE,
965968
RSC_VERSION,

‎x86_64/corefreq-cli.c‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1349,6 +1349,20 @@ REASON_CODE SysInfoProc(Window *win,
13491349
23, hSpace, RO(Shm)->Proc.Features.Factory.Ratio ),
13501350
RefreshFactoryFreq );
13511351

1352+
if (RO(Shm)->Proc.Features.OC_Enable)
1353+
{
1354+
PUT( SCANKEY_NULL, attrib[!RO(Shm)->Proc.Features.OC_Lock],
1355+
width, 2, "%s%.*s[%7.*s]", RSC(OVERCLOCK).CODE(),
1356+
width - 12 - RSZ(OVERCLOCK), hSpace, 6,
1357+
RO(Shm)->Proc.Features.OC_Lock ?
1358+
RSC(LOCK).CODE() : RSC(UNLOCK).CODE() );
1359+
1360+
PUT( SCANKEY_NULL, attrib[3], width, 0,
1361+
"%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]",
1362+
17, hSpace, RSC(BIN).CODE(),
1363+
2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock,
1364+
23, hSpace, RO(Shm)->Proc.Features.Factory.Bins );
1365+
}
13521366
PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE());
13531367

13541368
PUT(SCANKEY_NULL, attrib[0], width, 3, "%s", RSC(PSTATE).CODE());
@@ -4439,6 +4453,16 @@ REASON_CODE SysInfoTech(Window *win,
44394453
NULL,
44404454
SCANKEY_NULL,
44414455
NULL
4456+
},
4457+
{
4458+
(unsigned int[]) { CRC_INTEL, 0 },
4459+
RO(Shm)->Proc.Technology.OC == 1,
4460+
2, "%s%.*sOC [%3s]",
4461+
RSC(TECHNOLOGIES_OC).CODE(), NULL,
4462+
width - 13 - RSZ(TECHNOLOGIES_OC),
4463+
NULL,
4464+
SCANKEY_NULL,
4465+
NULL
44424466
}
44434467
};
44444468
size_t idx;

‎x86_64/corefreqk.c‎

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2680,6 +2680,142 @@ static PROCESSOR_SPECIFIC *LookupProcessor(void)
26802680
return NULL;
26812681
}
26822682

2683+
static void Intel_FlexRatio(bool OC_ENABLED)
2684+
{
2685+
if (OC_ENABLED) {
2686+
static struct {
2687+
struct SIGNATURE Arch;
2688+
unsigned short grantFlex : 1-0,
2689+
experimental : 2-1,
2690+
freeToUse : 16-2;
2691+
} list[] = {
2692+
{_Core_Yonah, 0, 1, 0},
2693+
{_Core_Conroe, 0, 1, 0},
2694+
{_Core_Kentsfield, 0, 1, 0},
2695+
{_Core_Conroe_616, 0, 1, 0},
2696+
{_Core_Penryn, 0, 1, 0},
2697+
{_Core_Dunnington, 0, 1, 0},
2698+
2699+
{_Atom_Bonnell, 0, 1, 0}, /* 06_1C */
2700+
{_Atom_Silvermont, 0, 1, 0}, /* 06_26 */
2701+
{_Atom_Lincroft, 0, 1, 0}, /* 06_27 */
2702+
{_Atom_Clover_Trail, 0, 1, 0}, /* 06_35 */
2703+
{_Atom_Saltwell, 0, 1, 0}, /* 06_36 */
2704+
2705+
{_Silvermont_Bay_Trail, 0, 1, 0}, /* 06_37 */
2706+
2707+
{_Atom_Avoton, 0, 1, 0}, /* 06_4D */
2708+
{_Atom_Airmont, 0, 1, 0}, /* 06_4C */
2709+
{_Atom_Goldmont, 1, 1, 0}, /* 06_5C */
2710+
{_Atom_Sofia, 1, 1, 0}, /* 06_5D */
2711+
{_Atom_Merrifield, 1, 1, 0}, /* 06_4A */
2712+
{_Atom_Moorefield, 1, 1, 0}, /* 06_5A */
2713+
2714+
{_Nehalem_Bloomfield, 1, 1, 0}, /* 06_1A */
2715+
{_Nehalem_Lynnfield, 1, 1, 0}, /* 06_1E */
2716+
{_Nehalem_MB, 1, 1, 0}, /* 06_1F */
2717+
{_Nehalem_EX, 1, 1, 0}, /* 06_2E */
2718+
2719+
{_Westmere, 1, 1, 0}, /* 06_25 */
2720+
{_Westmere_EP, 1, 1, 0}, /* 06_2C */
2721+
{_Westmere_EX, 1, 1, 0}, /* 06_2F */
2722+
2723+
{_SandyBridge, 1, 1, 0}, /* 06_2A */
2724+
{_SandyBridge_EP, 1, 1, 0}, /* 06_2D */
2725+
2726+
{_IvyBridge, 1, 0, 0}, /* 06_3A */
2727+
{_IvyBridge_EP, 1, 1, 0}, /* 06_3E */
2728+
2729+
{_Haswell_DT, 1, 1, 0}, /* 06_3C */
2730+
{_Haswell_EP, 1, 1, 0}, /* 06_3F */
2731+
{_Haswell_ULT, 1, 1, 0}, /* 06_45 */
2732+
{_Haswell_ULX, 1, 1, 0}, /* 06_46 */
2733+
2734+
{_Broadwell, 1, 1, 0}, /* 06_3D */
2735+
{_Broadwell_D, 1, 1, 0}, /* 06_56 */
2736+
{_Broadwell_H, 1, 1, 0}, /* 06_47 */
2737+
{_Broadwell_EP, 1, 1, 0}, /* 06_4F */
2738+
2739+
{_Skylake_UY, 1, 1, 0}, /* 06_4E */
2740+
{_Skylake_S, 1, 1, 0}, /* 06_5E */
2741+
{_Skylake_X, 1, 1, 0}, /* 06_55 */
2742+
2743+
{_Xeon_Phi, 0, 1, 0}, /* 06_57 */
2744+
2745+
{_Kabylake, 1, 1, 0}, /* 06_9E */
2746+
{_Kabylake_UY, 1, 1, 0}, /* 06_8E */
2747+
2748+
{_Cannonlake_U, 1, 1, 0}, /* 06_66 */
2749+
{_Cannonlake_H, 1, 1, 0},
2750+
{_Geminilake, 1, 1, 0}, /* 06_7A */
2751+
{_Icelake_UY, 1, 1, 0}, /* 06_7E */
2752+
2753+
{_Icelake_X, 1, 1, 0},
2754+
{_Icelake_D, 1, 1, 0},
2755+
{_Sunny_Cove, 1, 1, 0},
2756+
{_Tigerlake, 1, 1, 0},
2757+
{_Tigerlake_U, 1, 1, 0}, /* 06_8C */
2758+
{_Cometlake, 1, 1, 0},
2759+
{_Cometlake_UY, 1, 1, 0},
2760+
{_Atom_Denverton, 1, 1, 0},
2761+
{_Tremont_Jacobsville, 1, 1, 0},
2762+
{_Tremont_Lakefield, 1, 1, 0},
2763+
{_Tremont_Elkhartlake, 1, 1, 0},
2764+
{_Tremont_Jasperlake, 1, 1, 0},
2765+
{_Sapphire_Rapids, 1, 1, 0},
2766+
{_Emerald_Rapids, 1, 1, 0},
2767+
{_Granite_Rapids_X, 1, 1, 0},
2768+
{_Granite_Rapids_D, 1, 1, 0},
2769+
{_Sierra_Forest, 1, 1, 0},
2770+
{_Grand_Ridge, 1, 1, 0},
2771+
{_Rocketlake, 1, 1, 0},
2772+
{_Rocketlake_U, 1, 1, 0},
2773+
{_Alderlake_S, 1, 1, 0}, /* 06_97 */
2774+
{_Alderlake_H, 1, 1, 0},
2775+
{_Alderlake_N, 1, 1, 0},
2776+
{_Meteorlake_M, 1, 1, 0},
2777+
{_Meteorlake_N, 1, 1, 0},
2778+
{_Meteorlake_S, 1, 1, 0},
2779+
{_Raptorlake, 1, 1, 0}, /* 06_B7 */
2780+
{_Raptorlake_P, 1, 1, 0},
2781+
{_Raptorlake_S, 1, 1, 0},
2782+
{_Lunarlake, 1, 1, 0}, /* 06_BD */
2783+
{_Arrowlake, 1, 1, 0}, /* 06_C6 */
2784+
{_Arrowlake_H, 1, 1, 0}, /* 06_C5 */
2785+
{_Arrowlake_U, 1, 1, 0}, /* 06_B5 */
2786+
{_Pantherlake, 1, 1, 0}, /* 06_CC */
2787+
{_Clearwater_Forest, 1, 1, 0} /* 06_DD */
2788+
};
2789+
const unsigned int ids = sizeof(list) / sizeof(list[0]);
2790+
unsigned int id;
2791+
for (id = 0; id < ids; id++) {
2792+
if ((list[id].Arch.ExtFamily == PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily)
2793+
&& (list[id].Arch.Family == PUBLIC(RO(Proc))->Features.Std.EAX.Family)
2794+
&& (list[id].Arch.ExtModel == PUBLIC(RO(Proc))->Features.Std.EAX.ExtModel)
2795+
&& (list[id].Arch.Model == PUBLIC(RO(Proc))->Features.Std.EAX.Model))
2796+
{
2797+
if (list[id].grantFlex) {
2798+
if (!list[id].experimental
2799+
|| (list[id].experimental
2800+
&& PUBLIC(RO(Proc))->Registration.Experimental))
2801+
{
2802+
FLEX_RATIO flexRegister = {.value = 0};
2803+
RDMSR(flexRegister, MSR_FLEX_RATIO);
2804+
PUBLIC(RO(Proc))->Features.OC_Enable = flexRegister.OC_ENABLED;
2805+
PUBLIC(RO(Proc))->Features.Factory.Bins = flexRegister.OC_BINS;
2806+
PUBLIC(RO(Proc))->Features.OC_Lock = flexRegister.OC_LOCK;
2807+
PUBLIC(RO(Proc))->Features.Factory.Overclock = \
2808+
ABS_FREQ_MHz( signed int,
2809+
PUBLIC(RO(Proc))->Features.Factory.Bins,
2810+
PUBLIC(RO(Proc))->Features.Factory.Clock );
2811+
}
2812+
}
2813+
break;
2814+
}
2815+
}
2816+
}
2817+
}
2818+
26832819
static int Intel_MaxBusRatio(PLATFORM_ID *PfID)
26842820
{
26852821
struct SIGNATURE whiteList[] = {
@@ -5904,6 +6040,8 @@ static PCI_CALLBACK IVB_IMC(struct pci_dev *dev)
59046040
pci_read_config_dword(dev, 0xe8,
59056041
&PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.value);
59066042

6043+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.OC_ENABLED == 1);
6044+
59076045
PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
59086046

59096047
return Router(dev, 0x48, 64, 0x8000, Query_SNB_IMC, 0);
@@ -6104,6 +6242,8 @@ static PCI_CALLBACK HSW_HOST(struct pci_dev *dev, ROUTER Query)
61046242
pci_read_config_dword(dev, 0xe8,
61056243
&PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.value);
61066244

6245+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.IVB_Cap.OC_ENABLED == 1);
6246+
61076247
PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
61086248

61096249
return Router(dev, 0x48, 64, 0x8000, Query, 0);
@@ -6345,6 +6485,8 @@ static PCI_CALLBACK SKL_HOST( struct pci_dev *dev,
63456485
pci_read_config_dword(dev, 0xec,
63466486
&PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_C.value);
63476487

6488+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.SKL_Cap_B.OC_ENABLED == 1);
6489+
63486490
SoC_SKL_VTD();
63496491

63506492
return Router(dev, 0x48, 64, wsize, Query, mc);
@@ -6408,6 +6550,8 @@ static PCI_CALLBACK ADL_HOST( struct pci_dev *dev,
64086550
pci_read_config_dword(dev, 0xf0,
64096551
&PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_E.value);
64106552

6553+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_B.OC_ENABLED == 1);
6554+
64116555
SoC_SKL_VTD();
64126556

64136557
return Router(dev, 0x48, 64, wsize, Query, mc);
@@ -6467,6 +6611,8 @@ static PCI_CALLBACK MTL_HOST( struct pci_dev *dev,
64676611
pci_read_config_dword(dev, 0xf0,
64686612
&PUBLIC(RO(Proc))->Uncore.Bus.MTL_Cap_E.value);
64696613

6614+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.MTL_Cap_B.OC_ENABLED == 1);
6615+
64706616
SoC_SKL_VTD();
64716617

64726618
return Router(dev, 0x48, 64, wsize, Query, mc);
@@ -6519,6 +6665,8 @@ static PCI_CALLBACK GLK_IMC(struct pci_dev *dev)
65196665
pci_read_config_dword(dev, 0xe8,
65206666
&PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_B.value);
65216667

6668+
Intel_FlexRatio(PUBLIC(RO(Proc))->Uncore.Bus.GLK_Cap_B.OC_ENABLED == 1);
6669+
65226670
SoC_SKL_VTD();
65236671

65246672
return Router(dev, 0x48, 64, 0x8000, Query_GLK_IMC, 0);

‎x86_64/coretypes.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2161,6 +2161,8 @@ typedef struct /* BSP CPUID features. */
21612161
CLOCK Clock;
21622162
unsigned int Freq,
21632163
Ratio;
2164+
signed int Bins,
2165+
Overclock;
21642166
struct {
21652167
unsigned int Interface;
21662168
union {
@@ -2213,7 +2215,9 @@ typedef struct /* BSP CPUID features. */
22132215
OSPM_EPP : 55-54,
22142216
ACPI_CST_CAP : 56-55,
22152217
ACPI_CST : 60-56, /* 15 CState sub-packages */
2216-
_pad64 : 64-60;
2218+
OC_Enable : 61-60,
2219+
OC_Lock : 62-61,
2220+
_pad64 : 64-62;
22172221
};
22182222
} FEATURES;
22192223

‎x86_64/intel_reg.h‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -669,11 +669,14 @@ typedef union
669669
{ /* MSR_FLEX_RATIO(0x194): Core 2 Extreme, i9-9900K, 11th Gen, 12th Gen*/
670670
unsigned long long value;
671671
struct
672-
{
672+
{ /* OC Ratio = BCLK ratio + OC_BINS */
673673
unsigned long long
674-
UnknownBits1 : 16-0,
675-
OC_BINS : 24-16, /* OC Ratio = BCLK ratio + OC_BINS */
676-
UnknownBits2 : 64-24;
674+
OC_VID : 8-0,
675+
UnknownBits1 : 16-8,
676+
OC_ENABLED : 17-16,
677+
OC_BINS : 20-17, /* 0:Disabled ... 7:Unlimited */
678+
OC_LOCK : 21-20,
679+
UnknownBits2 : 64-21;
677680
};
678681
} FLEX_RATIO;
679682

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