[Intel] Query the Overclocking bit (OC) from Capabilities

Author: cyring

x86_64/corefreq-cli-json.c

@@ -1541,6 +1541,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.IPU);
 			json_key(&s, "VPU");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.VPU);
+			json_key(&s, "OC");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Technology.OC);
 
 			json_end_object(&s);
 		}

x86_64/corefreq.h

@@ -375,7 +375,8 @@ typedef struct
 				HDCP		: 46-45,
 				IPU		: 47-46,
 				VPU		: 48-47,
-				_pad64		: 64-48;
+				OC		: 49-48,
+				_pad64		: 64-49;
 	} Technology;
 
 	struct {

x86_64/corefreqd.c

@@ -4416,7 +4416,8 @@ void IVB_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Uncore.Unit.DDR_Ver  = 3;
 	RO(Shm)->Uncore.Unit.DDR_Std  = RAM_STD_UNSPEC;
 
-	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.SNB_Cap.VT_d;
+	RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.SNB_Cap.IVB.VT_d;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.IVB_Cap.OC_ENABLED;
 }
 
 unsigned int DimmWidthToRows(unsigned int width)
@@ -4973,6 +4974,7 @@ void SKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.SKL_Cap_B.GMM_DIS;
 	RO(Shm)->Proc.Technology.IPU = !RO(Proc)->Uncore.Bus.SKL_Cap_B.IMGU_DIS;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.SKL_Cap_B.OC_ENABLED;
 }
 
 void RKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -5294,6 +5296,7 @@ void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.RKL_Cap_B.GNA_DIS;
 	RO(Shm)->Proc.Technology.HDCP= !RO(Proc)->Uncore.Bus.RKL_Cap_B.HDCPD;
 	RO(Shm)->Proc.Technology.IPU = !RO(Proc)->Uncore.Bus.RKL_Cap_B.IPU_DIS;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.RKL_Cap_B.OC_ENABLED;
 }
 
 void TGL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -5851,6 +5854,7 @@ void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.ADL_Cap_B.GNA_DIS;
 	RO(Shm)->Proc.Technology.HDCP= !RO(Proc)->Uncore.Bus.ADL_Cap_B.HDCPD;
 	RO(Shm)->Proc.Technology.IPU = !RO(Proc)->Uncore.Bus.ADL_Cap_B.IPU_DIS;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.ADL_Cap_B.OC_ENABLED;
 }
 
 void GLK_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
@@ -5874,6 +5878,7 @@ void GLK_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 
 	RO(Shm)->Proc.Technology.GNA = !RO(Proc)->Uncore.Bus.GLK_Cap_B.GMM_DIS;
 	RO(Shm)->Proc.Technology.IPU = !RO(Proc)->Uncore.Bus.GLK_Cap_B.IMGU_DIS;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.GLK_Cap_B.OC_ENABLED;
 }
 
 void GLK_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
@@ -6004,6 +6009,7 @@ void MTL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
 	RO(Shm)->Proc.Technology.HDCP= !RO(Proc)->Uncore.Bus.MTL_Cap_B.HDCPD;
 	RO(Shm)->Proc.Technology.IPU = !RO(Proc)->Uncore.Bus.MTL_Cap_B.IPU_DIS;
 	RO(Shm)->Proc.Technology.VPU = !RO(Proc)->Uncore.Bus.MTL_Cap_C.VPU_DIS;
+	RO(Shm)->Proc.Technology.OC = RO(Proc)->Uncore.Bus.MTL_Cap_B.OC_ENABLED;
 }
 
 void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))

x86_64/intel_reg.h

@@ -3828,7 +3828,8 @@ typedef union
 		ReservedBits4	: 25-24,
 		CACHESZ 	: 28-25, /* Cache Size Capability	*/
 		SMTCAP		: 29-28, /* SMT Capability		*/
-		ReservedBits5	: 32-29;
+		OC_ENABLED	: 30-29, /* 0: Overclocking is disabled */
+		ReservedBits5	: 32-30;
 	};
 } IVB_CAPID_B;	/* Chap. 2.5.39 CAPID0_B Capabilities B Register	*/
 
@@ -5046,7 +5047,8 @@ typedef union
 		ReservedBits7	: 25-24,
 		CACHESZ 	: 28-25,
 		SMTCAP		: 29-28,
-		ReservedBits8	: 31-29,
+		OC_ENABLED	: 30-29, /* 0: Overclocking is disabled */
+		ReservedBits8	: 31-30,
 		IMGU_DIS	: 32-31; /* Device 5 associated memory spaces */
 	};	/* Chap. 3.40 CAPID0_B Capabilities B Register		*/
 } SKL_CAPID_B;