FIB - MIRI 2015
Professor:
Roger Espasa
Authors:
David Trilla
Constantino Gómez
Cristóbal Ortega
Features:
- 5 Stages
- Instructions:
- Arithmetic operations
- Long operation (>7 cycles)
- Load word/byte
- BNZ
- Instruction/Data cache
- Data hazards
- Structural hazards
- Main memory implemented inside the top level
- Stall all the processor/Fetch and Decode stages