Some error fixes and restore backup multifile

examples/RISCV-Sail/example13b.s

@@ -0,0 +1,142 @@
+#
+# Creator (https://creatorsim.github.io/creator/)
+#
+
+.section .bss
+.align 8
+tohost:
+    .dword 0
+
+.section .text.init
+.globl _main
+
+kernel:
+    j reset_vector
+
+    syscall: 
+        li t0, 13
+        bgeu a7, t0, fail
+        addi t0, t0, -3
+        beq t0, a7, exit
+
+    csrr t0, mepc
+    addi t0, t0, 4
+    csrw mepc, t0
+    mret
+
+    exit:
+        fence
+        li gp, 1
+        li a0, 0
+        li a7, 10
+        j exception+4
+
+    fail: 
+        fence
+        beqz gp, fail+0x4
+        slli gp, gp, 1
+        ori gp, gp, 1
+        li a7, 10
+        mv a0, gp
+        j syscall
+
+    trap_vec:
+        csrr t5, mcause
+        li t6, 8
+        beq t5, t6, syscall
+        li t6, 9
+        beq t5, t6, syscall
+        li t6, 11
+        beq t5, t6, syscall
+        j exception
+
+    exception:
+        ori gp, gp, 1337
+        la t5, tohost
+        sw gp, 0(t5)
+        sw zero, 4(t5)
+
+        j exception
+
+    reset_vector:
+        li ra, 0
+        li sp, 0x3FFFFFFC
+        li gp, 0
+        li tp, 0
+        li t0, 0
+        li t1, 0
+        li t2, 0
+        li fp, 0
+        li s1, 0
+        li a0, 0
+        li a1, 0
+        li a2, 0
+        li a3, 0
+        li a4, 0
+        li a5, 0
+        li a6, 0
+        li a7, 0
+        li s2, 0
+        li s3, 0
+        li s4, 0
+        li s5, 0
+        li s6, 0
+        li s7, 0
+        li s8, 0
+        li s9, 0
+        li s10, 0
+        li s11, 0
+        li t3, 0
+        li t4, 0
+        li t5, 0
+        li t6, 0
+
+    initial: 
+        csrr a0, mhartid
+        bnez a0, initial
+        auipc t0, 0
+        addi t0, t0, 16
+        csrw mtvec, t0
+        csrwi mstatus, 8
+        auipc t0, 0
+        addi t0, t0, 16
+        csrw mtvec, t0
+        csrwi satp, 0
+
+        auipc t0, 0
+        addi t0, t0, 36
+        csrw mtvec, t0
+        addi t0, zero, 1
+        slli t0, t0, 0x1f
+        csrw pmpaddr0, t0
+        li t0, 31
+        csrwi mie, 0
+        auipc t0, 0
+        addi t0, t0, 20
+
+        csrwi medeleg, 0
+        csrwi mideleg, 0
+        la t0, trap_vec
+        csrw mtvec, t0
+        csrw mepc, t0
+        lui t0, 0x2
+        addi t0, t0, -2048
+        csrrc zero, mstatus, t0
+
+        csrr t0, mstatus
+        lui t1, 0xffffe
+        addi t1, t1, 2047
+        and t0, t0, t1
+        li t1, 0
+        slli t1, t1, 11
+        or t0, t0, t1
+        csrw mstatus, t0
+
+        la t0, _main
+        csrw mepc, t0
+        mret
+
+_main:
+
+    li a7, 10
+    ecall

examples/RISCV-Sail/list.json → examples/RISCV-Sail/list32.json

@@ -74,7 +74,7 @@
   {
     "name": "Example 13",
     "id": "e13",
-    "url":"examples/RISCV-Sail/example13.s",
+    "url":"examples/RISCV-Sail/example13a.s",
     "description": "Custom kernel"
   },
   {

examples/RISCV-Sail/list64.json

@@ -0,0 +1,86 @@
+[
+  {
+    "name": "Example 1",
+    "id": "e1",
+    "url":"examples/RISCV-Sail/example1.s",
+    "description": "Data Storage"
+  },
+  {
+    "name": "Example 2",
+    "id": "e2",
+    "url":"examples/RISCV-Sail/example2.s",
+    "description": "ALU operations"
+  },
+  {
+    "name": "Example 3",
+    "id": "e3",
+    "url":"examples/RISCV-Sail/example3.s",
+    "description": "Store/Load Data in Memory"
+  },
+  {
+    "name": "Example 4",
+    "id": "e4",
+    "url":"examples/RISCV-Sail/example4.s",
+    "description": "FPU operations"
+  },
+  {
+    "name": "Example 5",
+    "id": "e5",
+    "url":"examples/RISCV-Sail/example5.s",
+    "description": "Loop"
+  },
+  {
+    "name": "Example 6",
+    "id": "e6",
+    "url":"examples/RISCV-Sail/example6.s",
+    "description": "Branch"
+  },
+  {
+    "name": "Example 7",
+    "id": "e7",
+    "url":"examples/RISCV-Sail/example7.s",
+    "description": "Loop + Memory"
+  },
+  {
+    "name": "Example 8",
+    "id": "e8",
+    "url":"examples/RISCV-Sail/example8.s",
+    "description": "Vector instructions"
+  },
+  {
+    "name": "Example 9",
+    "id": "e9",
+    "url":"examples/RISCV-Sail/example9.s",
+    "description": "I/O Syscalls"
+  },
+  {
+    "name": "Example 10",
+    "id": "e10",
+    "url":"examples/RISCV-Sail/example10.s",
+    "description": "I/O Syscalls + Strings"
+  },
+  {
+    "name": "Example 11",
+    "id": "e11",
+    "url":"examples/RISCV-Sail/example11.s",
+    "description": "Subrutines"
+  },
+  {
+    "name": "Example 12",
+    "id": "e12",
+    "url":"examples/RISCV-Sail/example12.s",
+    "description": "Factorial"
+  },
+  {
+    "name": "Example 13",
+    "id": "e13",
+    "url":"examples/RISCV-Sail/example13b.s",
+    "description": "Custom kernel"
+  },
+  {
+    "name": "Example 14",
+    "id": "e14",
+    "url":"examples/RISCV-Sail/example14.s",
+    "description": "Use custom instruction"
+  }
+]

examples/example_set.json

@@ -72,7 +72,7 @@
     "name": "RISC-V Sail 32 Examples",
     "id": "default",
     "architecture": "RISC-V Sail 32 - Full Specification",
-    "url": "examples/RISCV-Sail/list.json",
+    "url": "examples/RISCV-Sail/list32.json",
     "description": "RISC-V Sail 32 examples"
   },
 
@@ -81,7 +81,7 @@
     "name": "RISC-V Sail 64 Examples",
     "id": "default",
     "architecture": "RISC-V Sail 64 - Full Specification",
-    "url": "examples/RISCV-Sail/list.json",
+    "url": "examples/RISCV-Sail/list64.json",
     "description": "RISC-V Sail 64 examples"
   }
 ]

src/core/assembler/sailAssembler/web/CNAssambler.mjs

@@ -16,6 +16,7 @@ import { show_notification } from "../../../../web/utils.mjs";
 import { assembly_files } from "@/web/components/assembly/MultifileEditor.mjs";
 
 let sailas, sailld, saildump = null;
+export const statecode = { codeerror: false };
 export var libs_to_load = [];
 var list_data_instructions = [];
 var list_user_instructions = [];
@@ -1034,7 +1035,7 @@ export async function SailCompile(files, libs){
   if (a !== -1) 
     assembly_files.value[a].code = files;
 
-
+  statecode.codeerror = false;
   vectoren = false;
   doubleen = false;
   priven = false; 
@@ -1196,6 +1197,9 @@ export async function SailCompile(files, libs){
   }
 
   outfile = await as(filesToCompile);
+  if (statecode.codeerror) {
+    return outfile;
+  }
   let elffile = await ld(outfile, libs);
   let outdump = await dump(elffile);
   // document.app.$data.v_length = 64;

src/core/assembler/sailAssembler/web/wasm/as-new.js

@@ -1,3 +1,4 @@
+import { statecode } from "../CNAssambler.mjs";
 let ofile = null;
 var Module = (() => {
   var _scriptDir = import.meta.url;
@@ -252,6 +253,21 @@ if (ENVIRONMENT_IS_NODE) {
 
 var out = Module["print"] || console.log.bind(console);
 
+var instErrExp = /^\.\/([^:]+):(\d+):\s*Error:\s*(.+)$/;
+var errstatus;
+
+Module["printErr"] = function (message) {
+  console.error(message);
+  let asmerror = message.match(instErrExp);
+
+  if (asmerror && !statecode.codeerror){
+    console.error(asmerror);
+    errstatus = {status: "error", msg: asmerror[1] + " at line " + asmerror[2] + ": " + asmerror[3]};
+    statecode.codeerror = true;
+  }
+
+};
+
 var err = Module["printErr"] || console.warn.bind(console);
 
 Object.assign(Module, moduleOverrides);
@@ -5792,14 +5808,20 @@ function run(args) {
 
 //  readyPromiseResolve(Module);
 //  return Module.ready;
-  return ofile;
+  if (!statecode.codeerror)
+    return ofile;
+  else 
+    return errstatus;
 }
 
 Module["run"] = run;
 
 function exit(status, implicit) {
-  ofile = FS.readFile("./out.o");
-  console.log(ofile);
+
+  if (!statecode.codeerror){
+    ofile = FS.readFile("./out.o");
+    console.log(ofile);
+  }
  EXITSTATUS = status;
  if (keepRuntimeAlive()) {
   if (!implicit) {

src/core/assembler/sailAssembler/web/wasm/as-new64.js

@@ -1,3 +1,4 @@
+import { statecode } from "../CNAssambler.mjs";
 let ofile = null;
 var Module = (() => {
   var _scriptName = import.meta.url;
@@ -202,6 +203,22 @@ if (ENVIRONMENT_IS_WEB || ENVIRONMENT_IS_WORKER) {
 
 var out = Module["print"] || console.log.bind(console);
 
+var instErrExp = /^\.\/([^:]+):(\d+):\s*Error:\s*(.+)$/;
+var errstatus;
+
+Module["printErr"] = function (message) {
+
+  let asmerror = message.match(instErrExp);
+
+  if (asmerror && !statecode.codeerror){
+    console.error(asmerror);
+    errstatus = {status: "error", msg: asmerror[1] + " at line " + asmerror[2] + ": " + asmerror[3]};
+    statecode.codeerror = true;
+  } else 
+    console.error(message);
+
+};
+
 var err = Module["printErr"] || console.error.bind(console);
 
 // Merge back in the overrides

src/core/executor/sailSimRV/wasm/riscv_sim_RV32.js

@@ -9,6 +9,7 @@ import { coreEvents } from "@/core/events.mts";
 import { show_notification } from "@/web/utils.mjs";
 import { reset_disable, instruction_disable, run_disable, stop_disable, isFinished  } from "@/web/utils.mjs";
 import { architecture } from "../../../core.mjs";
+import { clearAllRegisterGlows } from "@/core/register/registerGlowState.mjs";
 
 
 export var userMode32 = false;
@@ -866,6 +867,9 @@ var Module = (() => {
 
       if (instMatch && (parseInt(instMatch[3], 16) >= pc_min && parseInt(instMatch[3], 16) <= pc_max )){
         userMode32 = true;
+
+        clearAllRegisterGlows();
+        coreEvents.emit("step-about-to-execute");
         if (inside_function)
           check_call_convention_temp_regs(instMatch);