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Fix right shift bit one bug #49

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merged 1 commit into from
Sep 10, 2024
Merged

Fix right shift bit one bug #49

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2 changes: 1 addition & 1 deletion chip8/cpu.py
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Original file line number Diff line number Diff line change
Expand Up @@ -699,7 +699,7 @@ def right_shift_reg(self):
self.v[0xF] = bit_one
self.last_op = f"SHR V{x:01X}"
else:
bit_one = self.v[x] & 0x1
bit_one = self.v[y] & 0x1
self.v[x] = self.v[y] >> 1
self.v[0xF] = bit_one
self.last_op = f"SHR V{x:01X}, V{y:01X}"
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9 changes: 9 additions & 0 deletions test/test_chip8cpu.py
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Original file line number Diff line number Diff line change
Expand Up @@ -399,6 +399,15 @@ def test_right_shift_reg(self):
self.assertEqual(self.cpu.v[x], shifted_val)
self.assertEqual(self.cpu.v[0xF], bit_zero)

def test_right_shift_reg_y_bug(self):
self.cpu.shift_quirks = False
self.cpu.operand = 0x0120
self.cpu.v[1] = 0
self.cpu.v[2] = 1
self.cpu.right_shift_reg()
self.assertEqual(0, self.cpu.v[1])
self.assertEqual(1, self.cpu.v[0xF])

def test_subtract_reg_from_reg1(self):
for x in range(0xF):
for y in range(0xF):
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