treewide: Schnova a reduced complexity out-of-order core

[Stefan-Odermatt]

Overview

This branch contains all files used to develop, test, and evaluate the Schnova core.

Hardware

The hardware implementation is located in hw/schnova. The top-level module is defined in the schnova.sv SystemVerilog file.

Key features of the core include:

• Configurable instruction fetch width. The number of instructions fetched per cycle must be a power of two.

• Configurable numbers of integer and floating-point physical registers.

• Support for two physical-register release mechanisms:

  • Reorder-buffer-based release, with a configurable number of reorder buffer entries.
  • Reference-counting-based release.

• Single-issue, in-order execution during normal operation.

• Automatic transition to superscalar, out-of-order execution when an frep.o hardware-loop instruction is fetched.

• Support for hardware loops in single-issue mode through the frep.i instruction.

• Configurable load-store units through a CSR, allowing each LSU to accept load instructions, store instructions, or both.

Testing

Software tests are located in sw/tests. Most of the existing Schnizo tests were reused, and two additional tests were added to cover branches inside hardware loops.

To run the complete test suite for a specific core configuration, use:

tests/schnova.yaml

A tracer similar to the existing Schnizo tracer was also implemented.

Evaluation

The core was evaluated in terms of:

• Performance
• Area
• Timing
• Power

All evaluation scripts, configurations, and results are located in experiments/schnova.