``` Example SOURCE_FILE : ADDI X0, XZR, #3; BL fact; B Exit; fact: SUBI SP, SP, #8; STUR LR, [SP, #4]; STUR X0, [SP, #0]; SUBIS X9, X0, #1; B.GE L1; ADDI X1, XZR, #1; ADDI SP, SP, #8; BR LR; L1: SUBI X0, X0, #1; BL fact; LDUR X0, [SP, #0]; LDUR LR, [SP, #4]; ADDI SP, SP, #8; ADD X1, X0, X1; BR LR; Exit:; ``` `ADD X1, X0, X1;` should be `MUL X1, X0, X1`