Acknowledgement: Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani, Dmitriy Fedorov, "StocNoC: Accelerating Stochastic Models Through Reconfigurable Network-on-Chip Architectures," In Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), pp. 361-375, April 2020. (DOI)
You can also find the paper on ResearchGate (link).
Spreading dynamics of many real-world processes lean heavily on the topological characteristics of the underlying contact network. With the rapid temporal and spatial evolution of complex inter-connected networks, microscopic modeling and stochastic simulation of individual-based interactions have become challenging in both, time and state space. Driven by the surge to reduce the time complexity associated with system behavior analysis over different network structures, we propose a network-on-chip (NoC) based FPGA solution called StocNoC. The proof of concept is supported by the design, implementation and evaluation of the classical heterogeneous susceptible-infected-susceptible (SIS) epidemic model on a scalable NoC. The steady-state results from the proposed implementation for the fractions of susceptible and infected nodes are shown to be comparable to those acquired from software simulations, but in a significantly shorter time period. Analogous to network information diffusion, implementation of the SIS model and its variants will be beneficial to foresee possible epidemic outbreaks earlier in time and expedite control decisions.
Users can implement the StocNoC design and simulate it using Vivado simulator. Please open the Vivado project (2018.2 version) and choose the appropriate test bench to simulate it.