Implement RISC-V port

[wkozaczuk]

This is more of an epic than a single issue, as it will take a bit of effort and individual issues, to get it done. In essence, this effort could be broken into the following pieces:

• modify main makefile and the build script to support the new arch
• modify scripts/loader.py to support debugging
• enable musl support (the version of musl OSv was lately upgraded), should support RISC-V (I think)
• implement arch/riscv64/*-arch.* and RISC-V specific modules, this is probably the key and most difficult item
• implement any RISC-V specific drivers (hopefully virtio should work)
• update all places with #ifdef __aarch64__ and/or #ifdef __x86_64__ and add necessary support for RISC-V
• many other things I have forgotten or I am not aware of

I believe QEMU supports running emulated RISC-V on x86 so that is where we could start.

BTW it would be cool to make OSv run on Fabrice Bellard's Tiny EMU which supports RISC-V.

PS. If anyone wants to add good resources about RISC-V, feel free.

[wkozaczuk]

• Some good blog about RISC-V - https://www.sifive.com/blog/all-aboard-part-0-introduction
• Interrupts - https://five-embeddev.com/baremetal/interrupts/
• Timer - https://five-embeddev.com/baremetal/timer/