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PriorityMux drops arguments if input sequences are not the same size
bug
good first issue
An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#4444
opened Oct 4, 2024 by
jackkoenig
Lexical scope is not properly checked for ports of submodules
bug
#4405
opened Sep 18, 2024 by
jackkoenig
bundleWithABoolProbe := 0.U.asTypeOf(bundleWithABoolProbe) results in illegal firrtl
bug
#4388
opened Sep 10, 2024 by
mwachs5
Modules with
chisel3.experimental.Analog
ports generate error using ChiselSim
bug
#4202
opened Jun 21, 2024 by
carlosedp
DataView of an Empty Module throws java.lang.IndexOutOfBoundsException
bug
#3203
opened Apr 25, 2023 by
seldridge
Reflective naming will override the name given by naming plugin
bug
#2554
opened Jun 1, 2022 by
jackkoenig
Exception in thread "main" firrtl.FirrtlInternalException: No width: UnknownType
bug
#2482
opened Apr 12, 2022 by
dsw
multidimensional arrays with ValidIO lead to incorrect inference of the direction
bug
#2054
opened Jul 26, 2021 by
sequencer
ChiselEnum: cannot use .asUInt.litValue to get the litValue
bug
feature request
Feature
New feature, will be included in release notes
usability
Mixing ChiselStage with ChirrtlEmitter does not work in 3.4.0-RC2
bug
#1592
opened Sep 18, 2020 by
jackkoenig
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