Feedback Request: Drawing Cells for Magic

.gitignore

@@ -0,0 +1,2 @@
+StdCellLib*.tgz
+*/__pycache__

.gitlab-ci.yml

@@ -0,0 +1,31 @@
+default:
+  image:
+    name: leviathanch/libresilicon-tools:latest 
+    entrypoint: [""]
+
+stages:
+  - build
+
+# Standard Cell Lib Targets:
+
+sky130_lib_3v3:
+  stage: build
+  script: . ~/.venv/bin/activate && make sky130_lib_3v3
+  artifacts:
+    paths:
+      - sky130_lib_3v3
+
+gf180_lib_3v3:
+  stage: build
+  script: . ~/.venv/bin/activate && make gf180_lib_3v3
+  artifacts:
+    paths:
+      - gf180_lib_3v3
+
+ihp_sg13g2_lib_1v8:
+  stage: build
+  script: . ~/.venv/bin/activate && make ihp_sg13g2_lib_1v8
+  artifacts:
+    paths:
+      - ihp_sg13g2_lib_1v8
+

Catalog/.gitignore

@@ -0,0 +1,9 @@
+*.mag 
+*.cell
+*.svg
+*.sp
+*.pxi
+!INV.cell
+__pycache__
+libresilicon.lib
+libresilicon.lef

Catalog/AND4.cell

@@ -1,13 +1,14 @@
-.DESCRIPTION "a 4-input AND gate"
-.SEE_ALSO "NAND3 - a 3-input Not-AND (or NAND) gate"
-.ORDER "Gate Drain Source MOSFET"
-A Y vdd pmos
-B Y vdd pmos
-C Y vdd pmos
-D Y vdd pmos
-Y Z vdd pmos
-A Y 2 nmos
-B 2 4 nmos
-C 4 6 nmos
-D 6 gnd nmos
-Y Z gnd nmos
+.AUTOGENERATED by Popcorn Tcl Script
+.inputs A B C D
+.outputs Z
+.ORDER "MOSFET Gate Drain Source"
+pmos A Y vdd
+pmos B Y vdd
+pmos C Y vdd
+pmos D Y vdd
+pmos Y Z vdd
+nmos A Y 1
+nmos B 1 2
+nmos C 2 3
+nmos D 3 gnd
+nmos Y Z gnd

Catalog/AOI21.cell

@@ -1,9 +1,8 @@
-.DESCRIPTION "a 2-1-input AND-OR-Invert gate"
-.SEE_ALSO "AOI21 - a 2-1-input AND-OR-Invert gate"
-.ORDER "Gate Drain Source MOSFET"
-A Y 1 pmos
-B 1 vdd pmos
-B1 1 vdd pmos
-A Y gnd nmos
-B Y 2 nmos
-B1 2 gnd nmos
+.AUTOGENERATED by Popcorn Tcl Script
+.inputs A A1
+.outputs Y
+.ORDER "MOSFET Gate Drain Source"
+pmos A Y vdd
+pmos A1 Y vdd
+nmos A Y 1
+nmos A1 1 gnd

Catalog/AOI31.cell

@@ -1,11 +1,13 @@
 .DESCRIPTION "a 3-1-input AND-OR-Invert gate"
 .SEE_ALSO "AOI31 - a 3-1-input AND-OR-Invert gate"
-.ORDER "Gate Drain Source MOSFET"
-A Y 1 pmos
-B 1 vdd pmos
-B1 1 vdd pmos
-B2 1 vdd pmos
-A Y gnd nmos
-B Y 2 nmos
-B1 2 3 nmos
-B2 3 gnd nmos
+.inputs A B B1 B2
+.outputs Y
+.ORDER "MOSFET Gate Drain Source"
+pmos A Y 1
+pmos B 1 vdd
+pmos B1 1 vdd
+pmos B2 1 vdd
+nmos A Y gnd
+nmos B Y 2
+nmos B1 2 3
+nmos B2 3 gnd

Catalog/ASYNC1.cell

@@ -0,0 +1,16 @@
+.AUTOGENERATED by spice2cell script from ASYNC1.spice
+.inputs A B
+.outputs C CN
+.ORDER "MOSFET Gate Drain Source"
+nmos B CN net3
+pmos A net4 VDD
+pmos B CN net4
+pmos A net1 VDD
+pmos B net1 VDD
+pmos C CN net1
+pmos CN C VDD
+nmos C CN net2
+nmos A net3 GND
+nmos B net2 GND
+nmos A net2 GND
+nmos CN C GND

Catalog/ASYNC2.cell

@@ -0,0 +1,12 @@
+.AUTOGENERATED by spice2cell script from ASYNC2.spice
+.inputs A B
+.outputs C CN
+.ORDER "MOSFET Gate Drain Source"
+nmos C CN GND
+pmos A net1 VDD
+pmos B CN net1
+pmos CN C VDD
+pmos C CN VDD
+nmos B CN net2
+nmos A net2 GND
+nmos CN C GND

Catalog/ASYNC3.cell

@@ -0,0 +1,16 @@
+.AUTOGENERATED by spice2cell script from ASYNC3.spice
+.inputs A B
+.outputs C CN
+.ORDER "MOSFET Gate Drain Source"
+nmos B CN net2
+nmos A net2 GND
+nmos A CN net1
+nmos CN C GND
+nmos B net1 GND
+nmos C net2 net1
+pmos B CN net3
+pmos A net3 VDD
+pmos B net4 VDD
+pmos A CN net4
+pmos CN C VDD
+pmos C net4 net3

Catalog/GNUmakefile

@@ -17,7 +17,8 @@
 #
 #   ////////////////////////////////////////////////////////////////
 #
-#   Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+#   Copyright (c)   2018, 2019 by
+#                   chipforge - <popcorn@nospam.chipforge.org>
 #   All rights reserved.
 #
 #       This Standard Cell Library is licensed under the Libre Silicon
@@ -51,11 +52,19 @@ RM ?=           rm -f
 TAR ?=          tar -zh
 DATE :=         $(shell date +%Y%m%d)
 
-#   project tools
+#   project settings
 
-POPCORN ?=      ../Tools/tcl/popcorn
-CELLS =         INV.cell NAND2.cell NAND3.cell AND4.cell NOR2.cell NOR3.cell OR4.cell
-LIMIT =         4
+CELLS =
+
+#   Attention! limit/buffer changes will impact cell catalog
+
+LIMIT ?=        5
+BUFFER ?=       $(LIMIT)    # recommended, but free to reduce
+LEVEL ?=        $(LIMIT)    # hack for fencing expand algorithmen
+DESCR ?=        '?'
+
+#POPCORN ?=      ../Tools/tcl/popcorn
+POPCORN ?=      ../Tools/popcorn/popcorn -l $(LEVEL) -b $(BUFFER) -D $(DESCR)
 
 #   ----------------------------------------------------------------
 #               DEFAULT TARGETS
@@ -72,36 +81,165 @@ help:
 	$(ECHO) "    help       - print this help screen"
 	$(ECHO) "    clean      - clean up all intermediate files"
 	$(ECHO) ""
-	$(ECHO) "    catalog    - compile catalog cells"
+	$(ECHO) "    catalog    - compile *all* catalog cells (see list below)"
+	$(ECHO) "    cell CELL=<cell> - compile up to dedicated catalog cell"
+	$(ECHO) ""
+	$(ECHO) "-------------------------------------------------------------------"
+	$(ECHO) "    available cells [limit=" $(LIMIT) "+ buffer=" $(BUFFER)"]:"
+	$(ECHO) "-------------------------------------------------------------------"
+	$(ECHO) ""
+	$(ECHO) $(CELLS)
 	$(ECHO) ""
-
 
 .PHONY: clean
 clean:
 #	$(RM) *.aux *.idx *.log *.toc *.out
+	$(RM) $(CELLS)
+	#$(RM) AND4.cell NAND2.cell NAND3.cell NOR2.cell NOR3.cell OR4.cell
+	$(RM) *.usage *.mag *.svg *.ext *.res.ext *.spice *.nodes *.sp *.sim *.al *.res.lump *.png *.err *.log *.libtemplate *.lib *.truthtable.html *.truthtable.v *.truthtable.txt outputlib/*.gds outputlib/*.lef outputlib/*.mag debuglib/* *.running *.mag.drc *.drc *.predrc *.done *.lef *_debug.oas *_debug.gds *.drc.tcl outputlib/*.oas
 
 #   ----------------------------------------------------------------
-#               DOCUMENTATION TARGETS
+#               CELL TARGETS
 #   ----------------------------------------------------------------
 
+#   include makefile with highest number of (allowed) stacked transistors
+
+ifeq ($(LIMIT),2)
+    include stacked2_cells.mk
+else
+ifeq ($(LIMIT),3)
+    include stacked3_cells.mk
+else
+ifeq ($(LIMIT),4)
+    include stacked4_cells.mk
+else
+ifeq ($(LIMIT),5)
+    include stacked5_cells.mk
+endif
+endif
+endif
+endif
+
 .PHONY: catalog
-catalog:    $(CELLS)
+catalog:    $(CELLS) 
+
+.PHONY: layout
+#layout: libresilicon.sp libresilicon.lef libresilicon.lib demoboard.mag doc/StdCellLib.pdf demoboard.svg
+layout: libresilicon.sp libresilicon.lef demoboard.mag doc/StdCellLib.pdf demoboard.svg
 
-AND4.cell: NAND3.cell
-	$(POPCORN) -l $(LIMIT) -n nand -c $@ -b $(LIMIT) $< 
+libresilicon.sp: *.cell ../Tech/librecell_tech.py ../Tools/perl/cell2spice.pl ../Tools/perl/librecells.pl ../Tech/nmos.sp
+	echo "Generating the cells $(CELLS)"
+	../Tools/perl/cell2spice.pl
+	../Tools/perl/librecells.pl
 
-NAND2.cell: INV.cell
-	$(POPCORN) -l $(LIMIT) -n nand -c $@ $<
+demoboard.mag: *.cell libresilicon.sp
+	perl ../Tools/perl/demoboard.pl >demoboard.mag
 
-NAND3.cell: NAND2.cell
-	$(POPCORN) -l $(LIMIT) -n nand -c $@ $<
+.PHONY: buildreport
+buildreport:
+	bash ../Tools/reporter.sh
 
-NOR2.cell: INV.cell
-	$(POPCORN) -l $(LIMIT) -n nor -c $@ $<
+libresilicon.lef: *.cell libresilicon.sp
+	../Tools/perl/lefgen.pl outputlib/*.lef >libresilicon.lef
 
-NOR3.cell: NOR2.cell
-	$(POPCORN) -l $(LIMIT) -n nor -c $@ $< 
+%.lib: %.sp
+	../Tools/perl/librecells_charlib.pl $< $@
 
-OR4.cell: NOR3.cell
-	$(POPCORN) -l $(LIMIT) -n nor -b $(LIMIT) -c $@ $<
+#libresilicon.lib: *.lib
+#	../Tools/perl/libgen.pl >libresilicon.libtemplate
+#	rm -f libresilicon.lib
+#	libertymerge -b libresilicon.libtemplate -o libresilicon.lib -u *.lib
 
+
+.PHONY: qflow
+qflow:	libresilicon.lef libresilicon.lib
+	sudo mkdir -p /usr/local/share/qflow/tech/ls050
+	sudo cp libresilicon.lef /usr/local/share/qflow/tech/ls050/ls050_stdcells.lef
+	sudo cp libresilicon.lib /usr/local/share/qflow/tech/ls050/ls05_stdcells.lib
+
+#AND4.cell: NAND3.cell
+#	$(POPCORN) -l $(LIMIT) -n nand -c $@ -b $(LIMIT) $< 
+#
+#NAND2.cell: INV.cell
+#	$(POPCORN) -l $(LIMIT) -n nand -c $@ $<
+#
+#NAND3.cell: NAND2.cell
+#	$(POPCORN) -l $(LIMIT) -n nand -c $@ $<
+#
+#AOI21.cell: INV.cell
+#	$(POPCORN) -l $(LIMIT) -n aoi -c $@ $<
+#
+#OAI21.cell: INV.cell
+#	$(POPCORN) -l $(LIMIT) -n oai -c $@ $<
+#
+#NOR2.cell: INV.cell
+#	$(POPCORN) -l $(LIMIT) -n nor -c $@ $<
+#
+#NOR3.cell: NOR2.cell
+#	$(POPCORN) -l $(LIMIT) -n nor -c $@ $< 
+#
+#OR4.cell: NOR3.cell
+#	$(POPCORN) -l $(LIMIT) -n nor -c $@ -b $(LIMIT) $<
+
+doc/StdCellLib.pdf: *.cell libresilicon.sp
+#	doc/docu.sh
+
+.PHONY: importQflow
+importQflow:
+	../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/gscl45nm/gscl45nm.sp
+	../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu018/osu018_stdcells.sp
+	../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu035/osu035_stdcells.sp
+	../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu050/osu050_stdcells.sp
+	../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu018/osu018_stdcells.sp
+	../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu035/osu035_stdcells.sp
+	../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu050/osu050_stdcells.sp
+
+mags=$(wildcard *.mag)
+svgs=$(mags:.mag=.svg)
+
+.PHONY: svg
+svg: $(svgs)
+
+test:
+	echo For debugging run "export PySpiceLogLevel=DEBUG" before make
+	lctime --debug --liberty libresilicon.lib \
+	--include ../Tech/libresilicon.m \
+	--spice INV.spice \
+	--cell INV \
+	--output INV.lib
+	libertyviz -l INV.lib --cell INV --pin Y --related-pin A --table cell_rise
+	libertymerge -b libresilicon.lib -o output_liberty.lib -u INV.lib AND2X1.lib
+
+test2:
+	/usr/local/bin/lctime --debug --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \
+	--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \
+	--spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \
+	--cell AND2X1 \
+	--output /tmp/and2x1.lib
+	libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_rise &
+	libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin B --table rise_transition &
+	libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_fall &
+	libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin B --table fall_transition &
+
+
+%.svg : %.mag
+	perl ../Tools/perl/mag2svg.pl $@
+
+%.truthtable.v : %.cell
+	perl ../Tools/perl/truthtable.pl --format=verilog $^ >$@
+
+%.truthtable.txt : %.cell
+	perl ../Tools/perl/truthtable.pl --format=text $^ >$@
+
+%.truthtable.html : %.cell
+	perl ../Tools/perl/truthtable.pl --format=html $^ >$@
+
+.PHONY: charter
+charter:
+	perl ../Tools/perl/charter2caravel.pl
+
+
+.PHONY: cell
+cell:       $(CELL)
+
+INV: INV.cell