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Merge patch series "riscv: Separate vendor extensions from standard e…
…xtensions" Charlie Jenkins <charlie@rivosinc.com> says: All extensions, both standard and vendor, live in one struct "riscv_isa_ext". There is currently one vendor extension, xandespmu, but it is likely that more vendor extensions will be added to the kernel in the future. As more vendor extensions (and standard extensions) are added, riscv_isa_ext will become more bloated with a mix of vendor and standard extensions. This also allows each vendor to be conditionally enabled through Kconfig. * b4-shazam-merge: riscv: cpufeature: Extract common elements from extension checking riscv: Introduce vendor variants of extension helpers riscv: Add vendor extensions to /proc/cpuinfo riscv: Extend cpufeature.c to detect vendor extensions Link: https://lore.kernel.org/r/20240719-support_vendor_extensions-v3-0-0af7587bbec0@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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menu "Vendor extensions" | ||
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config RISCV_ISA_VENDOR_EXT | ||
bool | ||
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menu "Andes" | ||
config RISCV_ISA_VENDOR_EXT_ANDES | ||
bool "Andes vendor extension support" | ||
select RISCV_ISA_VENDOR_EXT | ||
default y | ||
help | ||
Say N here if you want to disable all Andes vendor extension | ||
support. This will cause any Andes vendor extensions that are | ||
requested by hardware probing to be ignored. | ||
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If you don't know what to do here, say Y. | ||
endmenu | ||
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endmenu |
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/* SPDX-License-Identifier: GPL-2.0-only */ | ||
/* | ||
* Copyright 2024 Rivos, Inc | ||
*/ | ||
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#ifndef _ASM_VENDOR_EXTENSIONS_H | ||
#define _ASM_VENDOR_EXTENSIONS_H | ||
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#include <asm/cpufeature.h> | ||
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#include <linux/array_size.h> | ||
#include <linux/types.h> | ||
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/* | ||
* The extension keys of each vendor must be strictly less than this value. | ||
*/ | ||
#define RISCV_ISA_VENDOR_EXT_MAX 32 | ||
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struct riscv_isavendorinfo { | ||
DECLARE_BITMAP(isa, RISCV_ISA_VENDOR_EXT_MAX); | ||
}; | ||
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struct riscv_isa_vendor_ext_data_list { | ||
bool is_initialized; | ||
const size_t ext_data_count; | ||
const struct riscv_isa_ext_data *ext_data; | ||
struct riscv_isavendorinfo per_hart_isa_bitmap[NR_CPUS]; | ||
struct riscv_isavendorinfo all_harts_isa_bitmap; | ||
}; | ||
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extern struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[]; | ||
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extern const size_t riscv_isa_vendor_ext_list_size; | ||
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/* | ||
* The alternatives need some way of distinguishing between vendor extensions | ||
* and errata. Incrementing all of the vendor extension keys so they are at | ||
* least 0x8000 accomplishes that. | ||
*/ | ||
#define RISCV_VENDOR_EXT_ALTERNATIVES_BASE 0x8000 | ||
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#define VENDOR_EXT_ALL_CPUS -1 | ||
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bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsigned int bit); | ||
#define riscv_cpu_isa_vendor_extension_available(cpu, vendor, ext) \ | ||
__riscv_isa_vendor_extension_available(cpu, vendor, RISCV_ISA_VENDOR_EXT_##ext) | ||
#define riscv_isa_vendor_extension_available(vendor, ext) \ | ||
__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \ | ||
RISCV_ISA_VENDOR_EXT_##ext) | ||
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static __always_inline bool riscv_has_vendor_extension_likely(const unsigned long vendor, | ||
const unsigned long ext) | ||
{ | ||
if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) | ||
return false; | ||
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) | ||
return __riscv_has_extension_likely(vendor, | ||
ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); | ||
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return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); | ||
} | ||
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static __always_inline bool riscv_has_vendor_extension_unlikely(const unsigned long vendor, | ||
const unsigned long ext) | ||
{ | ||
if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) | ||
return false; | ||
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) | ||
return __riscv_has_extension_unlikely(vendor, | ||
ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE); | ||
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return __riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, ext); | ||
} | ||
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static __always_inline bool riscv_cpu_has_vendor_extension_likely(const unsigned long vendor, | ||
int cpu, const unsigned long ext) | ||
{ | ||
if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) | ||
return false; | ||
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && | ||
__riscv_has_extension_likely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) | ||
return true; | ||
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return __riscv_isa_vendor_extension_available(cpu, vendor, ext); | ||
} | ||
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static __always_inline bool riscv_cpu_has_vendor_extension_unlikely(const unsigned long vendor, | ||
int cpu, | ||
const unsigned long ext) | ||
{ | ||
if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) | ||
return false; | ||
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && | ||
__riscv_has_extension_unlikely(vendor, ext + RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) | ||
return true; | ||
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return __riscv_isa_vendor_extension_available(cpu, vendor, ext); | ||
} | ||
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#endif /* _ASM_VENDOR_EXTENSIONS_H */ |
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/* SPDX-License-Identifier: GPL-2.0 */ | ||
#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_ANDES_H | ||
#define _ASM_RISCV_VENDOR_EXTENSIONS_ANDES_H | ||
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#include <asm/vendor_extensions.h> | ||
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#include <linux/types.h> | ||
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#define RISCV_ISA_VENDOR_EXT_XANDESPMU 0 | ||
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/* | ||
* Extension keys should be strictly less than max. | ||
* It is safe to increment this when necessary. | ||
*/ | ||
#define RISCV_ISA_VENDOR_EXT_MAX_ANDES 32 | ||
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extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_andes; | ||
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#endif |
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