Skip to content

Commit

Permalink
[InstCombine] Duplicate tests for logical and/or (NFC)
Browse files Browse the repository at this point in the history 
This replicates existing and/or tests to also test variants using
select. This should help us get a more accurate view on which
optimizations we're missing if we disable the select -> and/or
fold.
  • Loading branch information
@nikic
nikic committed Jan 12, 2021
1 parent f706486 commit fb063c9
Show file tree
Hide file tree
Showing 50 changed files with 10,673 additions and 238 deletions.
37 changes: 37 additions & 0 deletions llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,3 +42,40 @@ cond_true: ; preds = %newFuncRoot
br i1 %bothcond, label %bb27.exitStub, label %cond_next23.exitStub
}

define i1 @print_pgm_cond_true_logical(i32 %tmp12.reload, i32* %tmp16.out) {
; CHECK-LABEL: @print_pgm_cond_true_logical(
; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label [[COND_TRUE:%.*]]
; CHECK: bb27.exitStub:
; CHECK-NEXT: store i32 [[TMP16:%.*]], i32* [[TMP16_OUT:%.*]], align 4
; CHECK-NEXT: ret i1 true
; CHECK: cond_next23.exitStub:
; CHECK-NEXT: store i32 [[TMP16]], i32* [[TMP16_OUT]], align 4
; CHECK-NEXT: ret i1 false
; CHECK: cond_true:
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr [17 x i32], [17 x i32]* @r, i32 0, i32 [[TMP12_RELOAD:%.*]]
; CHECK-NEXT: [[TMP16]] = load i32, i32* [[TMP15]], align 4
; CHECK-NEXT: [[TMP16_OFF:%.*]] = add i32 [[TMP16]], 31
; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[TMP16_OFF]], 62
; CHECK-NEXT: br i1 [[TMP0]], label [[BB27_EXITSTUB:%.*]], label [[COND_NEXT23_EXITSTUB:%.*]]
;
newFuncRoot:
br label %cond_true

bb27.exitStub: ; preds = %cond_true
store i32 %tmp16, i32* %tmp16.out
ret i1 true

cond_next23.exitStub: ; preds = %cond_true
store i32 %tmp16, i32* %tmp16.out
ret i1 false

cond_true: ; preds = %newFuncRoot
%tmp15 = getelementptr [17 x i32], [17 x i32]* @r, i32 0, i32 %tmp12.reload ; <i32*> [#uses=1]
%tmp16 = load i32, i32* %tmp15 ; <i32> [#uses=4]
%tmp18 = icmp slt i32 %tmp16, -31 ; <i1> [#uses=1]
%tmp21 = icmp sgt i32 %tmp16, 31 ; <i1> [#uses=1]
%bothcond = select i1 %tmp18, i1 true, i1 %tmp21 ; <i1> [#uses=1]
br i1 %bothcond, label %bb27.exitStub, label %cond_next23.exitStub
}

11 changes: 11 additions & 0 deletions llvm/test/Transforms/InstCombine/2007-03-13-CompareMerge.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,3 +13,14 @@ define i1 @test(i32 %c.3.i, i32 %d.292.2.i) {
%sel_tmp80 = or i1 %tmp266.i, %tmp276.i
ret i1 %sel_tmp80
}

define i1 @test_logical(i32 %c.3.i, i32 %d.292.2.i) {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: [[TMP1:%.*]] = icmp sle i32 [[C_3_I:%.*]], [[D_292_2_I:%.*]]
; CHECK-NEXT: ret i1 [[TMP1]]
;
%tmp266.i = icmp slt i32 %c.3.i, %d.292.2.i
%tmp276.i = icmp eq i32 %c.3.i, %d.292.2.i
%sel_tmp80 = select i1 %tmp266.i, i1 true, i1 %tmp276.i
ret i1 %sel_tmp80
}
11 changes: 11 additions & 0 deletions llvm/test/Transforms/InstCombine/2007-05-10-icmp-or.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,3 +12,14 @@ define i1 @test(i32 %tmp9) {
ret i1 %bothcond
}

define i1 @test_logical(i32 %tmp9) {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: [[TMP20:%.*]] = icmp ugt i32 [[TMP9:%.*]], 255
; CHECK-NEXT: ret i1 [[TMP20]]
;
%tmp20 = icmp ugt i32 %tmp9, 255 ; <i1> [#uses=1]
%tmp11.not = icmp sgt i32 %tmp9, 255 ; <i1> [#uses=1]
%bothcond = select i1 %tmp20, i1 true, i1 %tmp11.not ; <i1> [#uses=1]
ret i1 %bothcond
}

11 changes: 11 additions & 0 deletions llvm/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,3 +14,14 @@ define i1 @test(i32 %In) {
ret i1 %V
}

define i1 @test_logical(i32 %In) {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[IN:%.*]], 1
; CHECK-NEXT: ret i1 [[C2]]
;
%c1 = icmp sgt i32 %In, -1
%c2 = icmp eq i32 %In, 1
%V = select i1 %c1, i1 %c2, i1 false
ret i1 %V
}

13 changes: 13 additions & 0 deletions llvm/test/Transforms/InstCombine/2008-01-13-AndCmpCmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,16 @@ define i1 @test(i32 %c84.17) {
%tmp2703 = and i1 %tmp2696, %tmp2699 ; <i1> [#uses=1]
ret i1 %tmp2703
}

define i1 @test_logical(i32 %c84.17) {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: [[TMP2696:%.*]] = icmp ne i32 [[C84_17:%.*]], 34
; CHECK-NEXT: [[TMP2699:%.*]] = icmp sgt i32 [[C84_17]], -1
; CHECK-NEXT: [[TMP2703:%.*]] = and i1 [[TMP2696]], [[TMP2699]]
; CHECK-NEXT: ret i1 [[TMP2703]]
;
%tmp2696 = icmp ne i32 %c84.17, 34
%tmp2699 = icmp sgt i32 %c84.17, -1
%tmp2703 = select i1 %tmp2696, i1 %tmp2699, i1 false
ret i1 %tmp2703
}
25 changes: 25 additions & 0 deletions llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,3 +27,28 @@ bb74: ; preds = %entry
bb80: ; preds = %entry
ret float 0.000000e+00
}

define float @test_logical(float %x, x86_fp80 %y) nounwind readonly {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
; CHECK-NEXT: [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TMP67]], [[TMP71]]
; CHECK-NEXT: br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
; CHECK: bb74:
; CHECK-NEXT: ret float 0.000000e+00
; CHECK: bb80:
; CHECK-NEXT: ret float 0.000000e+00
;
entry:
%tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000 ; <i1> [#uses=1]
%tmp71 = fcmp uno float %x, 0.000000e+00 ; <i1> [#uses=1]
%bothcond = select i1 %tmp67, i1 true, i1 %tmp71 ; <i1> [#uses=1]
br i1 %bothcond, label %bb74, label %bb80

bb74: ; preds = %entry
ret float 0.000000e+00

bb80: ; preds = %entry
ret float 0.000000e+00
}
11 changes: 11 additions & 0 deletions llvm/test/Transforms/InstCombine/2008-06-21-CompareMiscomp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,14 @@ define i1 @test(i32 %In) {
ret i1 %V
}

define i1 @test_logical(i32 %In) {
; CHECK-LABEL: @test_logical(
; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[IN:%.*]], 15
; CHECK-NEXT: ret i1 [[C2]]
;
%c1 = icmp ugt i32 %In, 13
%c2 = icmp eq i32 %In, 15
%V = select i1 %c1, i1 %c2, i1 false
ret i1 %V
}

37 changes: 37 additions & 0 deletions llvm/test/Transforms/InstCombine/2008-08-05-And.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,3 +38,40 @@ okay:
incompatible:
ret void
}

define void @f_logical(i8* %x) nounwind {
; CHECK-LABEL: @f_logical(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[BB:%.*]]
; CHECK: bb:
; CHECK-NEXT: [[L1:%.*]] = load i8, i8* [[X:%.*]], align 1
; CHECK-NEXT: [[S1:%.*]] = add i8 [[L1]], -6
; CHECK-NEXT: [[C1:%.*]] = icmp ugt i8 [[S1]], 2
; CHECK-NEXT: [[S2:%.*]] = add i8 [[L1]], -10
; CHECK-NEXT: [[C2:%.*]] = icmp ugt i8 [[S2]], 2
; CHECK-NEXT: [[A1:%.*]] = and i1 [[C1]], [[C2]]
; CHECK-NEXT: br i1 [[A1]], label [[INCOMPATIBLE:%.*]], label [[OKAY:%.*]]
; CHECK: okay:
; CHECK-NEXT: ret void
; CHECK: incompatible:
; CHECK-NEXT: ret void
;
entry:
br label %bb

bb:
%g1 = getelementptr i8, i8* %x, i32 0
%l1 = load i8, i8* %g1, align 1
%s1 = sub i8 %l1, 6
%c1 = icmp ugt i8 %s1, 2
%s2 = sub i8 %l1, 10
%c2 = icmp ugt i8 %s2, 2
%a1 = select i1 %c1, i1 %c2, i1 false
br i1 %a1, label %incompatible, label %okay

okay:
ret void

incompatible:
ret void
}
17 changes: 17 additions & 0 deletions llvm/test/Transforms/InstCombine/2012-02-28-ICmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,3 +20,20 @@ define i1 @f1(i32 %x) {
%e = and i1 %b, %d
ret i1 %e
}

define i1 @f1_logical(i32 %x) {
; CHECK-LABEL: @f1_logical(
; CHECK-NEXT: [[A:%.*]] = trunc i32 [[X:%.*]] to i8
; CHECK-NEXT: [[B:%.*]] = icmp ne i8 [[A]], 0
; CHECK-NEXT: [[C:%.*]] = and i32 [[X]], 16711680
; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[C]], 0
; CHECK-NEXT: [[E:%.*]] = and i1 [[B]], [[D]]
; CHECK-NEXT: ret i1 [[E]]
;
%a = trunc i32 %x to i8
%b = icmp ne i8 %a, 0
%c = and i32 %x, 16711680
%d = icmp ne i32 %c, 0
%e = select i1 %b, i1 %d, i1 false
ret i1 %e
}
47 changes: 47 additions & 0 deletions llvm/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,3 +50,50 @@ return: ; preds = %if.else, %if.then
ret i32 %retval.0
}

define i32 @func_logical(i8* %c, i8* %f) nounwind uwtable readnone noinline ssp {
; CHECK-LABEL: @func_logical(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[D:%.*]] = alloca i8, align 1
; CHECK-NEXT: store i8 0, i8* [[D]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8* [[D]], [[C:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[CMP2:%.*]] = icmp ule i8* [[D]], [[F:%.*]]
; CHECK-NEXT: [[NOT_CMP1:%.*]] = icmp uge i8* [[C]], [[F]]
; CHECK-NEXT: [[DOTCMP2:%.*]] = and i1 [[CMP2]], [[NOT_CMP1]]
; CHECK-NEXT: br label [[RETURN:%.*]]
; CHECK: if.else:
; CHECK-NEXT: [[CMP5:%.*]] = icmp uge i8* [[D]], [[F]]
; CHECK-NEXT: [[NOT_CMP3:%.*]] = icmp ule i8* [[C]], [[F]]
; CHECK-NEXT: [[DOTCMP5:%.*]] = and i1 [[CMP5]], [[NOT_CMP3]]
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: [[RETVAL_0_IN:%.*]] = phi i1 [ [[DOTCMP2]], [[IF_THEN]] ], [ [[DOTCMP5]], [[IF_ELSE]] ]
; CHECK-NEXT: [[RETVAL_0:%.*]] = zext i1 [[RETVAL_0_IN]] to i32
; CHECK-NEXT: ret i32 [[RETVAL_0]]
;
entry:
%d = alloca i8, align 1
store i8 0, i8* %d, align 1
%cmp = icmp ugt i8* %d, %c
br i1 %cmp, label %if.else, label %if.then

if.then: ; preds = %entry
%cmp2 = icmp ule i8* %d, %f
%not.cmp1 = icmp uge i8* %c, %f
%.cmp2 = select i1 %cmp2, i1 %not.cmp1, i1 false
%land.ext = zext i1 %.cmp2 to i32
br label %return

if.else: ; preds = %entry
%cmp5 = icmp uge i8* %d, %f
%not.cmp3 = icmp ule i8* %c, %f
%.cmp5 = select i1 %cmp5, i1 %not.cmp3, i1 false
%land.ext7 = zext i1 %.cmp5 to i32
br label %return

return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %land.ext, %if.then ], [ %land.ext7, %if.else ]
ret i32 %retval.0
}

Loading

0 comments on commit fb063c9

Please sign in to comment.