Added instantiation templates and testbenches for selected modules

Author: pConst

ClkDivider.v

@@ -7,6 +7,15 @@
 //  Äåëèòåëü îñíîâíîãî òàêòîâîãî ñèãíàëà.
 //  Ïîçâîëÿåò ïîëó÷èòü ïðîèçâîäíûå ìåäëåííûå êëîêè ñèíõðîííûå ñ îïîðíûì.
 
+
+/*ClkDivider CD1 (
+    .clk(),
+    .nrst(),
+    .out()
+    );
+defparam CD1.WIDTH = 32;*/
+
+
 module ClkDivider(clk,nrst,out);
 
 input wire clk;

DeBounce.v

@@ -7,6 +7,16 @@
 //  Ðàáîòàåò ïî äâóì îòñ÷åòàì (ìåäëåííîãî) êëîêà. 
 //  Ïåðåêëþ÷àåòñÿ â îáà ñîñòîÿíèÿ ñ çàäåðæêîé íà äâà (ìåäëåííûõ) êëîêà
 
+
+/* DeBounce DB1 (
+	.clk(),
+	.nrst(),
+	.in(),
+	.out()
+	);
+defparam DB1.WIDTH = 1;*/
+
+
 module DeBounce(clk,nrst,in,out);
 
 input wire clk;

DynDelay.v

@@ -4,9 +4,19 @@
 //--------------------------------------------------------------------------------
 
 // INFO --------------------------------------------------------------------------------
-//  Ãåíåðàòîð çàäåðæêè ïðîèçâîëüíîãî ñèãíàëà
+//  ƒåíåðàòîð çàäåðæêè ïðîèçâîëüíîãî ñèãíàëà
 //  
 
+
+/* DynDelay DD1 (
+	.clk(),
+	.in(),
+	.sel(),
+	.out()
+	);
+defparam DD1.LENGTH = 8;*/
+
+
 //(* keep_hierarchy = "yes" *)
 module DynDelay(clk, in, sel, out);
 

EdgeDetect.v

@@ -8,15 +8,27 @@
 //  Âûäàåò åäèíè÷íûé èìïóëüñ ïî ôðîíòó, ñïàäó è êîìáèíèðîâàííûé
 //  Çàäåðæêà íà îäèí òàêò
 
-module EdgeDetect(clk, nrst, rising, falling, in, out);
+
+/*EdgeDetect ED1 (
+    .clk(),
+    .nrst(),
+    .in(),
+    .rising(),
+    .falling(),
+    .both()
+    );
+defparam ED1.WIDTH = 1;*/
+
+
+module EdgeDetect(clk, nrst, in, rising, falling, both);
 
 input wire clk;
 input wire nrst;
 
 input wire [(WIDTH-1):0] in;
 output reg [(WIDTH-1):0] rising = 0;
 output reg [(WIDTH-1):0] falling = 0;
-output wire [(WIDTH-1):0] out;
+output wire [(WIDTH-1):0] both;
 
 parameter WIDTH = 1;
 
@@ -38,6 +50,6 @@ always @ (posedge clk) begin
 end
 
 assign
-    out[(WIDTH-1):0] = rising[(WIDTH-1):0] | falling[(WIDTH-1):0];
+    both[(WIDTH-1):0] = rising[(WIDTH-1):0] | falling[(WIDTH-1):0];
 
 endmodule

Encoder.v

@@ -0,0 +1,44 @@
+//--------------------------------------------------------------------------------
+// Encoder.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  Îáðàáîòêà ñèãíàëîâ ñ ýíêîäåðà
+//
+
+/*Encoder E1(
+	.clk(),
+	.nrst(),
+	.incA(),
+	.incB(),
+	.plus1(),
+	.minus1()
+	);*/
+
+
+module Encoder(clk,nrst,incA,incB,plus1,minus1);
+
+input wire clk;
+input wire nrst;
+input wire incA, incB;		// present input values
+output reg plus1 = 0, minus1 = 0;
+
+reg bufA = 0, bufB = 0;		// previous inputvalues
+
+always @ (posedge clk) begin
+	if (~nrst) begin
+		bufA <= 0;
+		bufB <= 0;
+		plus1 <= 0;
+		minus1 <= 0;
+	end
+	else begin
+		plus1 <= (bufA^incB)&~(incA^bufB);
+		minus1 <= (incA^bufB)&~(bufA^incB);
+		bufA <= incA;
+		bufB <= incB;
+	end		// if
+end
+
+endmodule

Encoder_tb.v

@@ -0,0 +1,85 @@
+//--------------------------------------------------------------------------------
+// Encoder_test project, 201601
+// Main_tb.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//
+//
+
+`timescale 1ns / 1ps
+
+module Main_tb();
+
+reg clk200;
+initial begin
+        #0 clk200 = 1;
+        forever 
+            #2.5 clk200 = ~clk200;
+end
+
+reg rst;
+initial begin
+        #10.2 rst = 1;
+        #5 rst = 0;
+        //#10000;
+        forever begin
+            #9985 rst = ~rst;
+            #5 rst = ~rst;
+        end
+end
+wire nrst = ~rst;
+
+wire [31:0] DerivedClocks;
+ClkDivider CD1 (
+    .clk(clk200),
+    .nrst,
+    .out(DerivedClocks[31:0]));
+defparam CD1.WIDTH = 32;
+
+wire [31:0] E_DerivedClocks;
+EdgeDetect ED1 (
+    .clk(clk200),
+    .nrst,
+    .in(DerivedClocks[31:0]),
+    .rising(E_DerivedClocks[31:0]),
+    .falling(),
+    .both()
+    );
+defparam ED1.WIDTH = 32;
+
+wire [15:0] RandomNumber1;
+reg rst_once;
+initial begin
+        #10.2 rst_once = 1;
+        #5 rst_once = 0;
+end
+
+c_rand RNG1 (
+    .clk(clk200),
+    .rst(rst_once),
+    .reseed(1'b0),
+    .seed_val(DerivedClocks[15:0]),
+    .out(RandomNumber1[15:0]));
+
+reg start;
+initial begin
+        #100.2 start = 1;
+        #5 start = 0;
+end
+
+//=================================================
+
+wire p,m;
+Encoder E1(
+	.clk(clk200),
+	.nrst,
+	.incA(RandomNumber1[0]),
+	.incB(RandomNumber1[1]),
+	.plus1(p),
+	.minus1(m)
+	);
+    
+endmodule
+	

Main_TB.v

@@ -29,24 +29,36 @@ initial begin
             #5 rst = ~rst;
         end
 end
+wire nrst = ~rst;
 
 wire [31:0] DerivedClocks;
 ClkDivider CD1 (
     .clk(clk200),
-    .nrst(1'b1),
+    .nrst,
     .out(DerivedClocks[31:0]));
 defparam CD1.WIDTH = 32;
 
+wire [31:0] E_DerivedClocks;
+EdgeDetect ED1 (
+    .clk(clk200),
+    .nrst,
+    .in(DerivedClocks[31:0]),
+    .rising(E_DerivedClocks[31:0]),
+    .falling(),
+    .both()
+    );
+defparam ED1.WIDTH = 32;
+
 wire [15:0] RandomNumber1;
-reg rst1;
+reg rst_once;
 initial begin
-        #10.2 rst1 = 1;
-        #5 rst1 = 0;
+        #10.2 rst_once = 1;
+        #5 rst_once = 0;
 end
 
 c_rand RNG1 (
     .clk(clk200),
-    .rst(rst1),
+    .rst(rst_once),
     .reseed(1'b0),
     .seed_val(DerivedClocks[15:0]),
     .out(RandomNumber1[15:0]));
@@ -57,6 +69,8 @@ initial begin
         #5 start = 0;
 end
 
+//=================================================
+
 wire out1,out2;
 Main M(		// module under test
     TB_clk,~TB_clk,

PulseGen.v

@@ -7,6 +7,19 @@
 //  Ãåíåðàòîð èìïóëüñà
 //  Ðàáîòàåò íà÷èíàÿ ñ low_wdth = 1, high_wdth = 1
 
+
+/*PulseGen PG1(
+    .clk(),
+    .nrst(),
+    .low_wdth(),
+    .high_wdth(),
+    .rpt(),
+    .start(),
+    .busy(),
+    .out()
+    );*/
+
+
 module PulseGen(clk,nrst,low_wdth,high_wdth,rpt,start,busy,out);
 
 input wire clk;

PulseGen_tb.v

@@ -0,0 +1,67 @@
+//--------------------------------------------------------------------------------
+// PulseGen_test project, 201512
+// Main_tb.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//
+//
+
+`timescale 1ns / 1ps
+
+module Main_tb();
+
+reg clk200;
+initial begin
+        #0 clk200 = 1;
+        forever 
+            #2.5 clk200 = ~clk200;
+end
+
+reg rst;
+initial begin
+        #10.2 rst = 1;
+        #5 rst = 0;
+        //#10000;
+        forever begin
+            #9985 rst = ~rst;
+            #5 rst = ~rst;
+        end
+end
+
+wire [31:0] DerivedClocks;
+ClkDivider CD1 (
+    .clk(clk200),
+    .nrst(1'b1),
+    .out(DerivedClocks[31:0]));
+defparam CD1.WIDTH = 32;
+
+wire [15:0] RandomNumber1;
+reg rst1;
+initial begin
+        #10.2 rst1 = 1;
+        #5 rst1 = 0;
+end
+
+c_rand RNG1 (
+    .clk(clk200),
+    .rst(rst1),
+    .reseed(1'b0),
+    .seed_val(DerivedClocks[15:0]),
+    .out(RandomNumber1[15:0]));
+
+reg start;
+initial begin
+        #100.2 start = 1;
+        #5 start = 0;
+end
+
+wire busy1,out1;
+PulseGen PG1 (clk200,~rst,1,1,1'b1,start,busy1,out1);
+
+wire busy2,out2;
+PulseGen PG2 (clk200,~rst,{28'b0,RandomNumber1[3:0]},{28'b0,RandomNumber1[7:4]},1'b0,&RandomNumber1[2:0],busy2,out2);
+    
+endmodule
+	

README.md

@@ -5,17 +5,21 @@
 
 **/Advanced Synthesis Cookbook/**		useful code from Altera`s cookbook  
 
-*Main_TB.v**		- basic testbench template  
+**Main_TB.v**		- basic testbench template  
 
 **ClkDivider.v**		- wide reference clock divider  
 **DeBounce.v**		- two-cycle debounce for input buttons  
+**DynDelay.v**		- dynamic delay made on general-purpose trigger elements  
 **EdgeDetect.v**		- edge detector, gives one-tick pulses on every signal edge  
+**Encoder.v**		encoder input module
+**PulseGen.v**		- generates pulses with given width and delay  
 **ResetSet.v**		- SR trigger variant w/o metastable state, set dominates here  
 **SetReset.v**		- SR trigger variant w/o metastable state, reset dominates here  
+**SimplePulseGen.v**		- generates one-cycle pulse with given delay  
 **Synch.v**		- input syncnronizer (and also "static delay module"), standard way to get rid of metastability issues  
 
-**DynDelay.v**		- dynamic delay made on general-purpose trigger elements  
-**PulseGen.v**		- generates pulses with given width and delay  
-**SimplePulseGen.v**		- generates one-cycle pulse with given delay  
+Also added some simple testbenches for selected modules
+
 
+Author: Konstantin Pavlov, pavlovconst@gmail.com