Fixed error in Synch module

Author: pConst

README.md

@@ -12,6 +12,10 @@
 **EdgeDetect.v**		- edge detector, gives one-tick pulses on every signal edge  
 **ResetSet.v**		- SR trigger variant w/o metastable state, set dominates here  
 **SetReset.v**		- SR trigger variant w/o metastable state, reset dominates here  
-**Synch.v**		- input syncnronizer, standard way to get rid of metastability issues  
+**Synch.v**		- input syncnronizer (and also "static delay module"), standard way to get rid of metastability issues  
+
+**DynDelay.v**		- dynamic delay made on general-purpose trigger elements  
+**PulseGen.v**		- generates pulses with given width and delay  
+**SimplePulseGen.v**		- generates one-cycle pulse with given delay  
 
 

Synch.v

@@ -8,9 +8,10 @@
 //  Ñòàíäàðòíûé ìåòîä ïîäàâëåíèÿ ìåòàñòàáèëüíîñòè.
 
 //(* keep_hierarchy = "yes" *)
-module Synch(clk, in, out);		// aka "static delay"
+module Synch(clk, nrst, in, out);		// aka "static delay"
 
 input wire clk;
+input wire nrst;
 input wire [(WIDTH-1):0] in;
 output wire [(WIDTH-1):0] out;
 
@@ -20,11 +21,16 @@ parameter WIDTH = 1;    // independent channels
 (* keep = "true" *) reg [(LENGTH*WIDTH-1):0] data = 0;
 
 always @ (posedge clk) begin
-    data[(LENGTH*WIDTH-1):0] << WIDTH;
-	data[(WIDTH-1):0] <= in[(WIDTH-1):0];
+	if (~nrst) begin
+		data[(LENGTH*WIDTH-1):0] <= 0;
+	end
+	else begin
+        data[(LENGTH*WIDTH-1):0] <= data[(LENGTH*WIDTH-1):0] << WIDTH;
+        data[(WIDTH-1):0] <= in[(WIDTH-1):0];
+	end
 end
 
 assign
-    out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):(((LENGTH-1)*WIDTH)];
+    out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):((LENGTH-1)*WIDTH)];
 
 endmodule