UartExtreme rewrite and simulation done

Author: pConst

UartRxExtreme.v

@@ -5,7 +5,12 @@
 
 // INFO --------------------------------------------------------------------------------
 //  Extreme minimal UART receiver optimized for 20MHz/115200 data rate
-
+//  
+// CAUTION:
+// optimized for 20MHz/115200
+// rx_sample_cntr[7:0] does never stop, but reloads on sequense start condition
+// initial rx_sample_cntr[7:0] value has been made 255 instead of 257 to save one precious counter register
+// rx_busy and rx_done fall simultaneously 0,5 bit before stop bit time end
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
@@ -28,18 +33,20 @@ input wire clk;
 output reg [7:0] rx_data = 0;
 reg rx_data_9th_bit = 0;	// {rx_data[7:0],rx_data_9th_bit} is actually a shift register
 
-output wire rx_busy;
+output reg rx_busy = 0;     // sequence control is done by rx_busy and unique high logic state of rx_data_9th_bit register
 output wire rx_done;
 input wire rxd;
 
 
+// Falling edge detector
 reg rxd_prev = 0;
 always @ (posedge clk) begin
 	rxd_prev <= rxd;
 end
 wire start_bit_strobe = ~rx_busy && (~rxd & rxd_prev);
 
 
+// Sample counter
 reg [7:0] rx_sample_cntr = 0;
 always @ (posedge clk) begin
 	if (start_bit_strobe) begin
@@ -50,29 +57,27 @@ always @ (posedge clk) begin
 		end else begin
 			rx_sample_cntr[7:0] <= rx_sample_cntr[7:0] - 1;
 		end // rx_sample_cntr
-	end // ~rx_busy && start_bit_strobe
+	end // start_bit_strobe
 end
 wire rx_do_sample = (rx_sample_cntr[7:0] == 0);
 
-
+// Data shifting
 always @ (posedge clk) begin
 	if (start_bit_strobe) begin
 		{rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;
+		rx_busy <= 1;
 	end // start_bit_strobe
 
-	if (rx_do_sample) begin
-		if (~rx_done) begin
-			{rx_data[7:0],rx_data_9th_bit} <= {rxd,rx_data[7:0]};
+	if (rx_busy && rx_do_sample) begin
+		if (rx_data_9th_bit) begin
+		      rx_busy <= 0;
 		end else begin
-			rx_data[7:0] <= 0;
-			rx_data_9th_bit <= 0;
-		end	// ~rx_done
-	end // rx_do_sample
+		      {rx_data[7:0],rx_data_9th_bit} <= {rxd,rx_data[7:0]};
+		end
+	end // (rx_busy && rx_do_sample)
 end
 
 assign
-	rx_busy = |{rx_data[7:0],rx_data_9th_bit},
-	rx_done = rx_data_9th_bit && rx_do_sample && rxd;
+	rx_done = (rx_busy && rx_do_sample && rx_data_9th_bit) && rxd;
 
-
 endmodule

UartTxExtreme.v

@@ -5,10 +5,25 @@
 
 // INFO --------------------------------------------------------------------------------
 // Extreme minimal UART transmitter
+//  
+// CAUTION:
+// optimized for 20MHz/115200
+// tx_busy has been made asynchronous to tx_do_sample
+// tx_start has no internal protection and should be rised only when tx_busy is low
 
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
+reg [7:0] tx_sample_cntr = 0;
+always @ (posedge clk20) begin
+	if (tx_sample_cntr[7:0] == 0) begin
+		tx_sample_cntr[7:0] <= (173-1);
+	end else begin
+		tx_sample_cntr[7:0] <= tx_sample_cntr[7:0] - 1;
+	end
+end
+wire tx_do_sample = (tx_sample_cntr[7:0] == 0);
+
 UartTxExtreme UT1 (
     .clk(),
 	//.tx_do_sample(),
@@ -34,7 +49,6 @@ output reg txd = 1;
 
 
 reg [9:0] tx_shifter = 0;
-
 always @ (posedge clk) begin
 	if (tx_start) begin
 		tx_shifter[9:0] <= {1'b1,tx_data[7:0],1'b0};

UartTxExtreme_UartRxExtreme_tb.v

@@ -0,0 +1,109 @@
+//--------------------------------------------------------------------------------
+// SimWrapper.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//
+//
+
+`timescale 1ns / 1ps
+
+module SimWrapper();
+
+reg clk200;
+initial begin
+        #0 clk200 = 1;
+        forever 
+            #2.5 clk200 = ~clk200;
+end
+
+reg rst;
+initial begin
+        #10.2 rst = 1;
+        #5 rst = 0;
+        //#10000;
+        forever begin
+            #9985 rst = ~rst;
+            #5 rst = ~rst;
+        end
+end
+wire nrst = ~rst;
+
+reg rst_once;
+initial begin       // initializing non-X data before PLL starts
+        #10.2 rst_once = 1;
+        #5 rst_once = 0;
+end
+initial begin
+        #510.2 rst_once = 1;    // PLL starts at 500ns, clock appears, so doing the reset for modules
+        #5 rst_once = 0;
+end
+wire nrst_once = ~rst_once;
+
+wire [31:0] DerivedClocks;
+ClkDivider CD1 (
+    .clk(clk200),
+    .nrst(nrst_once),
+    .out(DerivedClocks[31:0]));
+defparam CD1.WIDTH = 32;
+
+wire [31:0] E_DerivedClocks;
+EdgeDetect ED1 (
+    .clk(clk200),
+    .nrst(nrst_once),
+    .in(DerivedClocks[31:0]),
+    .rising(E_DerivedClocks[31:0]),
+    .falling(),
+    .both()
+    );
+defparam ED1.WIDTH = 32;
+
+wire [15:0] RandomNumber1;
+c_rand RNG1 (
+    .clk(clk200),
+    .rst(rst_once),
+    .reseed(1'b0),
+    .seed_val(DerivedClocks[31:0]),
+    .out(RandomNumber1[15:0]));
+
+reg start;
+initial begin
+        #100.2 start = 1;
+        #5 start = 0;
+end
+
+
+
+reg [7:0] tx_sample_cntr = 0;
+
+always @ (posedge clk200) begin
+	if (tx_sample_cntr[7:0] == 0) begin
+		tx_sample_cntr[7:0] <= (173-1);
+	end else begin
+		tx_sample_cntr[7:0] <= tx_sample_cntr[7:0] - 1;
+	end
+end
+wire tx_do_sample = (tx_sample_cntr[7:0] == 0);
+
+wire txd_pin;
+wire txbusy_pin;
+
+UartTxExtreme UT1 (
+    .clk(clk200),
+	.tx_do_sample(tx_do_sample),
+	.tx_data(RandomNumber1[7:0]),
+	.tx_start(start),
+	.tx_busy(txbusy_pin),
+	.txd(txd_pin)
+    );
+
+UartRxExtreme UR1 (
+    .clk(clk200),
+	.rx_data(),
+	.rx_busy(),
+	.rx_done(),
+	.rxd(txd_pin)
+    );
+
+endmodule