Added extreme minimal UART implementations. Testing in progress

Author: pConst

README.md

@@ -3,8 +3,8 @@
 ####(licensed under CC BY-SA 4_0)
 
 
-**/Advanced Synthesis Cookbook/**		- useful code from Altera`s cookbook  
-**/KCPSM6_Release9_30Sept14/**		- Xilinx`s Picoblaze soft processor  
+**/Advanced Synthesis Cookbook/**		- useful code from Altera's cookbook  
+**/KCPSM6_Release9_30Sept14/**		- Xilinx's Picoblaze soft processor  
 **/pacoblaze-2.2/**		- version of Picoblaze adapted for Altera devices  
 
 **Main_tb.v**		- basic testbench template  
@@ -21,8 +21,11 @@
 **SimplePulseGen.v**		- generates one-cycle pulse with given delay  
 **StaticDelay.v**		- static delay made on Xilinx`s SRL16E primitives  
 **Synch.v**		- input synchronizer (and also "static delay module"), standard way to get rid of metastability issues  
+
 **UartRx.v**		- straightforward yet simple UART receiver implementation for FPGA written in Verilog  
 **UartTx.v**		- straightforward yet simple UART transmitter implementation for FPGA written in Verilog  
+**UartRxExtreme.v**		- extreme minimal UART receiver implementation for FPGA written in Verilog  
+**UartTxExtreme.v**		- extreme minimal UART transmitter implementation for FPGA written in Verilog  
 
 Also added some simple testbenches for selected modules
 

UartRx.v

@@ -6,14 +6,15 @@
 // INFO --------------------------------------------------------------------------------
 //  Straightforward yet simple UART receiver implementation for FPGA written in Verilog
 //  Expects at least one stop bit
+//  Features continuous data aquisition at BAUD levels up to CLK_HZ / 2
+//  Features early asynchronous 'busy' reset
 
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
 UartRx UR1 (
     .clk(),
     .nrst(),
-	
 	.rx_data(),
 	.rx_busy(),
 	.rx_done(),
@@ -36,74 +37,68 @@ input wire clk;
 input wire nrst;
 
 output reg [7:0] rx_data = 0;
+reg rx_data_9th_bit = 0;	// {rx_data[7:0],rx_data_9th_bit} is actually a shift register
+
 output reg rx_busy = 0;
-output reg rx_done = 0;		// read strobe
-output reg rx_err = 0;		// read strobe
+output wire rx_done;		// read strobe
+output wire rx_err;
 input wire rxd;
 
 
+Synch S (
+    .clk(clk),
+    .nrst(nrst),
+    .in(rxd),
+    .out(s_rxd)		// Synchronized rxd
+    );
+defparam S.LENGTH = 2;
+defparam S.WIDTH = 1;
+
+
 reg rxd_prev = 0;
 always @ (posedge clk) begin
 	if (~nrst) begin
 		rxd_prev <= 0;
 	end else begin
-		rxd_prev <= rxd;
+		rxd_prev <= s_rxd;
 	end
 end
-
-wire start_bit_strobe = ~rxd & rxd_prev;
+wire start_bit_strobe = ~s_rxd & rxd_prev;
 
 reg [15:0] rx_sample_cntr = (BAUD_DIVISOR_2 - 1);
 wire rx_do_sample = (rx_sample_cntr[15:0] == 0);
-reg [3:0] rx_data_cntr = 4'b1000;
-
 always @ (posedge clk) begin
 	if (~nrst) begin
-		rx_data[7:0] <= 0;
 		rx_busy <= 0;
-		rx_done <= 0;
-		rx_err <= 0;
-		rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 - 1);
-		rx_data_cntr[3:0] <= 4'b1000; 
 	end else begin
 		if (~rx_busy) begin
 			if (start_bit_strobe) begin
 				rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 3 - 1);		// wait for 1,5-bit period till next sample
-				rx_data[7:0] <= 0;
+				{rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;
 				rx_busy <= 1;
-				rx_done <= 0;
-				rx_err <= 0;
-				rx_data_cntr[3:0] <= 4'b1000;
 			end // start_bit_strobe
 		end else begin
 
 			if (rx_sample_cntr[15:0] == 0) begin
-				rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1);		// wait for 1-bit-period till next sample
+				rx_sample_cntr[15:0] <= (BAUD_DIVISOR_2 * 2 - 1);	// wait for 1-bit-period till next sample
 			end else begin
 				rx_sample_cntr[15:0] <= rx_sample_cntr[15:0] - 1;	// counting and sampling only when 'busy'
 			end
 
 			if (rx_do_sample) begin
-				if (rx_data_cntr[3:0] == 0)	begin	// do stop bit check
-					if (rxd) begin
-						rx_done <= 1;
-					end	else begin
-						rx_err <= 1;
-					end // rxd
-				end else begin						// do sample and shift data
-					rx_data[7:0] <= {rxd, rx_data[7:1]};
-					rx_data_cntr[3:0] <= rx_data_cntr[3:0] - 1;
-				end	// rx_data_cntr[3:0]
+				if (rx_data_9th_bit == 1) begin
+					rx_busy <= 0;		// early asynchronous 'busy' reset
+				end else begin
+					{rx_data[7:0],rx_data_9th_bit} <= {s_rxd, rx_data[7:0]};
+				end	//
 			end // rx_do_sample
 
-			if (rx_done || rx_err) begin
-				rx_busy <= 0;
-				rx_done <= 0;
-				rx_err <= 0;
-			end	// rx_done
-			
 		end	// ~rx_busy
 	end // ~nrst
 end
 
+assign
+	rx_done = rx_data_9th_bit && rx_do_sample && s_rxd,		// rx_done and rx_busy fall simultaneously
+	rx_err = rx_data_9th_bit && rx_do_sample && ~s_rxd;
+
 endmodule

UartRxExtreme.v

@@ -0,0 +1,78 @@
+//--------------------------------------------------------------------------------
+// UartRxExtreme.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  Extreme minimal UART receiver optimized for 20MHz/115200 data rate
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+UartRxExtreme UR1 (
+    .clk(),
+	.rx_data(),
+	.rx_busy(),
+	.rx_done(),
+	.rxd()
+    );
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module UartRxExtreme(clk, rx_data, rx_busy, rx_done, rxd);
+
+
+input wire clk;
+
+output reg [7:0] rx_data = 0;
+reg rx_data_9th_bit = 0;	// {rx_data[7:0],rx_data_9th_bit} is actually a shift register
+
+output wire rx_busy;
+output wire rx_done;
+input wire rxd;
+
+
+reg rxd_prev = 0;
+always @ (posedge clk) begin
+	rxd_prev <= rxd;
+end
+wire start_bit_strobe = ~rx_busy && (~rxd & rxd_prev);
+
+
+reg [7:0] rx_sample_cntr = 0;
+always @ (posedge clk) begin
+	if (start_bit_strobe) begin
+		rx_sample_cntr[7:0] <= (86 * 3 - 1) - 2;
+	end else begin
+		if (rx_sample_cntr[7:0] == 0) begin
+			rx_sample_cntr[7:0] <= (86 * 2 - 1);
+		end else begin
+			rx_sample_cntr[7:0] <= rx_sample_cntr[7:0] - 1;
+		end // rx_sample_cntr
+	end // ~rx_busy && start_bit_strobe
+end
+wire rx_do_sample = (rx_sample_cntr[7:0] == 0);
+
+
+always @ (posedge clk) begin
+	if (start_bit_strobe) begin
+		{rx_data[7:0],rx_data_9th_bit} <= 9'b100000000;
+	end // start_bit_strobe
+
+	if (rx_do_sample) begin
+		if (~rx_done) begin
+			{rx_data[7:0],rx_data_9th_bit} <= {rxd,rx_data[7:0]};
+		end else begin
+			rx_data[7:0] <= 0;
+			rx_data_9th_bit <= 0;
+		end	// ~rx_done
+	end // rx_do_sample
+end
+
+assign
+	rx_busy = |{rx_data[7:0],rx_data_9th_bit},
+	rx_done = rx_data_9th_bit && rx_do_sample && rxd;
+	
+
+endmodule

UartTx.v

@@ -6,14 +6,17 @@
 // INFO --------------------------------------------------------------------------------
 //  Straightforward yet simple UART transmitter implementation for FPGA written in Verilog
 //  One stop bit setting is hardcoded
+//  Features continuous data output at BAUD levels up to CLK_HZ / 2
+//  Features early asynchronous 'busy' set and reset to gain time to prepare new data
+//  If multiple UartTX instances should be inferred - make tx_sample_cntr logic common for all TX instances for effective chip area usage
 
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
 UartTx UT1 (
     .clk(),
     .nrst(),
-
+	//.tx_do_sample(),
 	.tx_data(),
 	.tx_start(),
 	.tx_busy(),
@@ -26,33 +29,34 @@ defparam UT1.BAUD = 9600;	// max. BAUD is CLK_HZ / 2
 
 
 module UartTx(clk, nrst, tx_data, tx_start, tx_busy, txd);
+//module UartTx(clk, nrst, tx_do_sample, tx_data, tx_start, tx_busy, txd);
 
 parameter CLK_HZ = 200_000_000;
 parameter BAUD = 9600;
 parameter BAUD_DIVISOR = CLK_HZ / BAUD;
 
 input wire clk;
 input wire nrst;
+//input wire tx_do_sample;
 
 input wire [7:0] tx_data;
 input wire tx_start;		// write strobe
 output reg tx_busy = 0;
 output reg txd = 1;
 
 
-reg [15:0] tx_sample_cntr = (BAUD_DIVISOR-1);
 reg [9:0] tx_shifter = 0;
-
+reg [15:0] tx_sample_cntr = 0;
 always @ (posedge clk) begin
 	if ((~nrst) || (tx_sample_cntr[15:0] == 0)) begin
 		tx_sample_cntr[15:0] <= (BAUD_DIVISOR-1);
 	end else begin
-		tx_sample_cntr[15:0] <= tx_sample_cntr[15:0] - 1'b1;
+		tx_sample_cntr[15:0] <= tx_sample_cntr[15:0] - 1;
 	end
 end
-
 wire tx_do_sample = (tx_sample_cntr[15:0] == 0);
 
+
 always @ (posedge clk) begin
 	if (~nrst) begin
 		tx_busy <= 0;
@@ -68,12 +72,11 @@ always @ (posedge clk) begin
 
 			if (tx_do_sample) begin		// next bit
 				{tx_shifter[9:0],txd} <= {tx_shifter[9:0],txd} >> 1;	// txd MUST change only on tx_do_sample although data may be loaded earlier
+				if (~|tx_shifter[9:1]) begin		// early asynchronous 'busy' reset
+					tx_busy <= 0;					// txd still holds data, but shifter is ready to get new info
+				end			
 			end	// tx_do_sample
 
-			if (~|tx_shifter[9:0]) begin		// asynchronous 'busy' reset
-				tx_busy <= 0;					// txd still holds data, but shifter is ready
-			end
-			
 		end	// ~tx_busy
 	end // ~nrst
 end

UartTxExtreme.v

@@ -0,0 +1,51 @@
+//--------------------------------------------------------------------------------
+// UartTxExtreme.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+// Extreme minimal UART transmitter
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+UartTxExtreme UT1 (
+    .clk(),
+	//.tx_do_sample(),
+	.tx_data(),
+	.tx_start(),
+	.tx_busy(),
+	.txd()
+    );
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module UartTxExtreme(clk, tx_do_sample, tx_data, tx_start, tx_busy, txd);
+
+
+input wire clk;
+input wire tx_do_sample;
+
+input wire [7:0] tx_data;
+input wire tx_start;
+output wire tx_busy;
+output reg txd = 1;
+
+
+reg [9:0] tx_shifter = 0;
+
+always @ (posedge clk) begin
+	if (tx_start) begin
+		tx_shifter[9:0] <= {1'b1,tx_data[7:0],1'b0};
+	end	// tx_start
+	
+	if (tx_do_sample) begin
+		{tx_shifter[9:0],txd} <= {tx_shifter[9:0],txd} >> 1;
+	end	// tx_do_sample
+end
+
+assign
+	tx_busy = |tx_shifter[9:1];
+
+endmodule