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xtensa: sign-extend scaled offsets in decodeOffset_* helpers #2997

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xtensa: sign-extend scaled offsets in decodeOffset_* helpers #2997

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44 changes: 13 additions & 31 deletions arch/Xtensa/XtensaDisassembler.c
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Original file line number Diff line number Diff line change
Expand Up @@ -788,72 +788,57 @@ static DecodeStatus decodeOffset_16_16Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isIntN(8, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0xf) != 0)
MCOperand_CreateImm0(Inst, (Imm << 4));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 4, 8));
return MCDisassembler_Success;
}

static DecodeStatus decodeOffset_256_8Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0x7) != 0)
MCOperand_CreateImm0(Inst, (Imm << 3));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 3, 11));
return MCDisassembler_Success;
}

static DecodeStatus decodeOffset_256_16Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0xf) != 0)
MCOperand_CreateImm0(Inst, (Imm << 4));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 4, 12));
return MCDisassembler_Success;
}

static DecodeStatus decodeOffset_256_4Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0x2) != 0)
MCOperand_CreateImm0(Inst, (Imm << 2));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 2, 10));
return MCDisassembler_Success;
}

static DecodeStatus decodeOffset_128_2Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(7, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0x1) != 0)
MCOperand_CreateImm0(Inst, (Imm << 1));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, (Imm << 1));
return MCDisassembler_Success;
}

static DecodeStatus decodeOffset_128_1Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(7, Imm) && "Invalid immediate",
MCDisassembler_Fail);
MCOperand_CreateImm0(Inst, (Imm));
return MCDisassembler_Success;
Expand All @@ -863,12 +848,9 @@ static DecodeStatus decodeOffset_64_16Operand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
CS_ASSERT_RET_VAL(isUIntN(6, Imm) && "Invalid immediate",
MCDisassembler_Fail);
if ((Imm & 0xf) != 0)
MCOperand_CreateImm0(Inst, (Imm << 4));
else
MCOperand_CreateImm0(Inst, (Imm));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 4, 10));
return MCDisassembler_Success;
}

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64 changes: 64 additions & 0 deletions tests/issues/issues.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6269,6 +6269,70 @@ test_cases:
regs_write: [ f8, f9, f7, f4 ]
groups: [ HasESP32S3Ops ]

-
input:
name: "Xtensa decodeOffset_64_16Operand sign extension"
bytes: [ 0x2f, 0x71, 0x01, 0x4e ]
arch: "CS_ARCH_XTENSA"
options: [ CS_MODE_XTENSA_ESP32, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
- asm_text: "ee.vmulas.u16.accx.ld.ip.qup q4, a2, -0xf0, q5, q6, q0, q1"
details:
xtensa:
operands:
- type: XTENSA_OP_REG
reg: q4
access: CS_AC_WRITE
- type: XTENSA_OP_REG
reg: a2
access: CS_AC_READ
- type: XTENSA_OP_IMM
imm: -0xf0
access: CS_AC_READ
- type: XTENSA_OP_REG
reg: q5
access: CS_AC_READ
- type: XTENSA_OP_REG
reg: q6
access: CS_AC_READ
- type: XTENSA_OP_REG
reg: q0
access: CS_AC_READ
- type: XTENSA_OP_REG
reg: q1
access: CS_AC_READ
regs_read: [ a2, q5, q6, q0, q1 ]
regs_write: [ q4 ]
groups: [ HasESP32S3Ops ]

-
input:
name: "Xtensa decodeOffset_128_2Operand offset scaling"
bytes: [ 0x74, 0xe0, 0xb5 ]
arch: "CS_ARCH_XTENSA"
options: [ CS_MODE_XTENSA_ESP32, CS_OPT_DETAIL ]
address: 0x0
expected:
insns:
- asm_text: "ee.vldbc.16.ip q7, a7, 0xc0"
details:
xtensa:
operands:
- type: XTENSA_OP_REG
reg: q7
access: CS_AC_WRITE
- type: XTENSA_OP_REG
reg: a7
access: CS_AC_READ
- type: XTENSA_OP_IMM
imm: 0xc0
access: CS_AC_READ
regs_read: [ a7 ]
regs_write: [ q7 ]
groups: [ HasESP32S3Ops ]

-
input:
name: "#2722 - CS_OPT_UNSIGNED is ignored for most archs"
Expand Down
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