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Merged
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Sep 5, 2023
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15d7f83
Refactor PPC module for auto-sync
Rot127 Jul 8, 2023
5205916
Update auto-sync scripts with changes introdduces with PPC update
Rot127 Jul 8, 2023
ebdd62f
Update additional files associated with PPC auto-sync update.
Rot127 Jul 8, 2023
405ba19
Add check for detail
Rot127 Jul 8, 2023
d232140
Add getFeatureBits call.
Rot127 Jul 8, 2023
39dc350
Fix reachable assert/segfault (also in LLVM).
Rot127 Jul 8, 2023
51df179
Remove INVALID entry which is already part of the generated data
Rot127 Jul 8, 2023
7223607
Handle memory operands printed via printOperand without setting mem o…
Rot127 Jul 8, 2023
09387bb
Set correct operand type of cr bit field.
Rot127 Jul 8, 2023
0d1db37
Remove debug string
Rot127 Jul 8, 2023
a57ffa1
Fix braces around initializer bug
Rot127 Jul 8, 2023
7cb368d
Add naive fuzzing code.
Rot127 Jul 8, 2023
ac787be
Add MT/MFSPR alias enum values
Rot127 Jul 8, 2023
8336458
Rename duplicate variable
Rot127 Jul 8, 2023
c5d9aee
Revert "Rename duplicate variable"
Rot127 Jul 8, 2023
762b508
Revert "Add naive fuzzing code."
Rot127 Jul 8, 2023
5d48271
Add missing operand printers
Rot127 Jul 20, 2023
bd97d98
Fix undefined behavior of shift by using uint64_t and fix build warni…
Rot127 Jul 20, 2023
a89cbfc
Add more MTSPR and MFSPR alias
Rot127 Jul 20, 2023
e5df497
Increment major version
Rot127 Jul 20, 2023
29abd76
Fix rebase blunder. Set correct header file location.
Rot127 Jul 24, 2023
c567ec7
Allow to patch also inc files without specifing the include guard.
Rot127 Jul 24, 2023
12e1357
Fix: Cutting first line.
Rot127 Jul 24, 2023
8d5e42e
Add feature to select between alias and real operand set.
Rot127 Jul 24, 2023
3b05ae2
Clearify documentation and fix incorrect SO predicates.
Rot127 Jul 25, 2023
4ca8fde
Save BI field separately from csX_bit.
Rot127 Jul 25, 2023
d876f73
Replace magic numbers with their enums.
Rot127 Jul 25, 2023
3a2185c
Add helper functions to test for branch cond flags.
Rot127 Jul 25, 2023
0064e01
Remove LI instruction (they are alias).
Rot127 Jul 25, 2023
f2238cb
Set constant zero as mem base if base reg == r0.
Rot127 Jul 25, 2023
b5e1b90
Replace tabs after mnemonic with space.
Rot127 Jul 26, 2023
5d0c547
Set ZERO register, not the value 0 for (RA|0) cases
Rot127 Jul 26, 2023
a01fef3
Add missing implicit write to LR.
Rot127 Jul 26, 2023
93e6915
Print implicity read/written registers.
Rot127 Jul 26, 2023
9ee7bb1
Remove unused code (was replaced with proper alias handling.)
Rot127 Jul 26, 2023
f7646d2
Fix S[LR]WI alias instructions.
Rot127 Jul 27, 2023
f11afcc
Handle hardcoded sldi alias.
Rot127 Jul 27, 2023
216eb47
Remove unused variable
Rot127 Jul 27, 2023
74a1271
Remove leading tabs
Rot127 Jul 27, 2023
58fbfa4
Check if detail ops shall be filled before insert_op
Rot127 Jul 27, 2023
00641b1
Replace branch alias defined as instructions with actual alias.
Rot127 Jul 29, 2023
7891d77
Remove additional space before alias mnemonic
Rot127 Jul 29, 2023
07277ef
Rename function to make it less similar to test_cr_bit and add harder…
Rot127 Jul 29, 2023
59fef92
Fix build of cstest ppc_detail.c
Rot127 Jul 30, 2023
1590b86
Reorder alias after change to td files.
Rot127 Jul 30, 2023
affa5af
Set correct type instruction decoding (fixes prefixed instructions.)
Rot127 Jul 31, 2023
f6ffa21
Add memory operand flags to prefix instructions.
Rot127 Jul 31, 2023
8235f42
Check for option to print register names without prefix.
Rot127 Jul 31, 2023
c14282b
Add check if PS mode is enabled.
Rot127 Jul 31, 2023
467358f
Revert "Increment major version"
Rot127 Jul 31, 2023
43cad57
Add READ_WRITE access attribute to fix build error.
Rot127 Aug 5, 2023
8d7aaeb
Run clang-format
Rot127 Aug 5, 2023
fbb39c2
Remove manipulation of cs option during tests.
Rot127 Aug 8, 2023
1d73395
Add NOREGNAME option to endocing tests.
Rot127 Aug 8, 2023
09d6343
Revert "ppc: fix suite/MC/PowerPC/ppc64-encoding.s.cs"
Rot127 Aug 8, 2023
8420dd7
Fix PPC alias instruction tests.
Rot127 Aug 8, 2023
16a5f36
Disable MSYNC feature.
Rot127 Aug 8, 2023
777b88d
Fix book-II instruction tests - Sets instructions as in LLVM
Rot127 Aug 8, 2023
0d1d15e
Add more ppc64 encoding tests.
Rot127 Aug 8, 2023
44ad6e2
Add AIXOS feature to not enabled list.
Rot127 Aug 8, 2023
a08bbf1
Add conditional branch alias which branch always.
Rot127 Aug 8, 2023
b8718c2
Add ppc64 encoding ext tests with new branch alias.
Rot127 Aug 8, 2023
1e92e9a
Add Book-III tests from LLVM
Rot127 Aug 8, 2023
31b59cf
Remove wrong branch alias and add tests for them.
Rot127 Aug 8, 2023
fb6b2ee
Add three more tests
Rot127 Aug 8, 2023
1aa62ad
Add BOOKE as mode.
Rot127 Aug 8, 2023
75923a1
Compile cstest with debug info
Rot127 Aug 8, 2023
a18fcf6
Add option to print % sign in front of register names.
Rot127 Aug 9, 2023
f882dff
Add support for S12 immediates of PS instructions.
Rot127 Aug 9, 2023
bed53d7
Add option to choose instruction detail set (between alias and real).
Rot127 Aug 9, 2023
8313842
Fix syntax/alias issuesin issues.cs
Rot127 Aug 9, 2023
a385d79
fix false usage of arm details.
Rot127 Aug 9, 2023
243823d
Update python constants.
Rot127 Aug 10, 2023
23e9796
Update python bindings with changes to PPC and cs_insn structs.
Rot127 Aug 10, 2023
3acd756
Check for more edge cases when memory operands are emitted via printO…
Rot127 Aug 10, 2023
4556561
Set correct values for the MCRegisterInfo struct.
Rot127 Aug 23, 2023
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16 changes: 10 additions & 6 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -253,19 +253,23 @@ if(CAPSTONE_PPC_SUPPORT)
arch/PowerPC/PPCModule.c
)
set(HEADERS_PPC
arch/PowerPC/PPCDisassembler.h
arch/PowerPC/PPCGenAsmWriter.inc
arch/PowerPC/PPCInstrInfo.h
arch/PowerPC/PPCInstPrinter.h
arch/PowerPC/PPCLinkage.h
arch/PowerPC/PPCMapping.h
arch/PowerPC/PPCMCTargetDesc.h
arch/PowerPC/PPCPredicates.h
arch/PowerPC/PPCRegisterInfo.h
arch/PowerPC/PPCGenAsmWriter.inc
arch/PowerPC/PPCGenRegisterName.inc
arch/PowerPC/PPCGenCSFeatureName.inc
arch/PowerPC/PPCGenCSMappingInsn.inc
arch/PowerPC/PPCGenCSMappingInsnOp.inc
arch/PowerPC/PPCGenCSMappingInsnName.inc
arch/PowerPC/PPCGenCSOpGroup.inc
arch/PowerPC/PPCGenDisassemblerTables.inc
arch/PowerPC/PPCMappingInsn.inc
arch/PowerPC/PPCMappingInsnName.inc
arch/PowerPC/PPCGenInstrInfo.inc
arch/PowerPC/PPCGenSubtargetInfo.inc
arch/PowerPC/PPCGenRegisterInfo.inc
arch/PowerPC/PPCGenInstrInfo.inc
)
set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
endif()
Expand Down
8 changes: 8 additions & 0 deletions MCInst.c
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,8 @@ void MCInst_Init(MCInst *inst)
inst->xAcquireRelease = 0;
for (int i = 0; i < MAX_MC_OPS; ++i)
inst->tied_op_idx[i] = -1;
inst->isAliasInstr = false;
inst->fillDetailOps = false;
}

void MCInst_clear(MCInst *inst)
Expand Down Expand Up @@ -280,3 +282,9 @@ uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
else
assert(0 && "Operand type not handled in this getter.");
}

void MCInst_setIsAlias(MCInst *MI, bool Flag) {
assert(MI);
MI->isAliasInstr = Flag;
MI->flat_insn->is_alias = Flag;
}
8 changes: 8 additions & 0 deletions MCInst.h
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,8 @@ struct MCInst {
cs_wasm_op wasm_data; // for WASM operand
MCRegisterInfo *MRI;
uint8_t xAcquireRelease; // X86 xacquire/xrelease
bool isAliasInstr; // Flag if this MCInst is an alias.
bool fillDetailOps; // If set, detail->operands gets filled.
};

void MCInst_Init(MCInst *inst);
Expand Down Expand Up @@ -163,4 +165,10 @@ bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);

uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum);

void MCInst_setIsAlias(MCInst *MI, bool Flag);

static inline bool MCInst_isAlias(const MCInst *MI) {
return MI->isAliasInstr;
}

#endif
3 changes: 3 additions & 0 deletions MCInstPrinter.c
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
#include <capstone/platform.h>

extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);

static bool testFeatureBits(const MCInst *MI, uint32_t Value)
{
Expand All @@ -15,6 +16,8 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
assert(0 && "Not implemented for current arch.");
case CS_ARCH_ARM:
return ARM_getFeatureBits(MI->csh->mode, Value);
case CS_ARCH_PPC:
return PPC_getFeatureBits(MI->csh->mode, Value);
}
}

Expand Down
58 changes: 58 additions & 0 deletions Mapping.c
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
/* Rot127 <unisono@quyllur.org>, 2022-2023 */

#include "Mapping.h"
#include "capstone/capstone.h"

// create a cache for fast id lookup
static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
Expand Down Expand Up @@ -311,3 +312,60 @@ const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
DEFINE_get_detail_op(arm, ARM);
DEFINE_get_detail_op(ppc, PPC);
DEFINE_get_detail_op(tricore, TriCore);

/// Returns true if for this architecture the
/// alias operands should be filled.
/// TODO: Replace this with a proper option.
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Do we have an issue for this?

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Not yet. I need to update AArch64 and ARM for it as well. Do this after or just before everything is updated to LLVM 17.

/// So it can be toggled between disas() calls.
bool map_use_alias_details(const MCInst *MI) {
assert(MI);
return !(MI->csh->detail_opt & CS_OPT_DETAIL_REAL);
}

/// Sets the setDetailOps flag to @p Val.
/// If detail == NULLit refuses to set the flag to true.
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typo?

void map_set_fill_detail_ops(MCInst *MI, bool Val) {
assert(MI);
if (!detail_is_set(MI)) {
MI->fillDetailOps = false;
return;
}

MI->fillDetailOps = Val;
}

/// Sets the instruction alias flags and the given alias id.
void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias) {
assert(MI);
MI->isAliasInstr = Val;
MI->flat_insn->is_alias = Val;
MI->flat_insn->alias_id = Alias;
}

/// Sets an alternative id for some instruction.
/// Or -1 if it fails.
/// You must add (<ARCH>_INS_ALIAS_BEGIN + 1) to the id to get the real id.
void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size) {
if (!MCInst_isAlias(MI))
return;

char alias_mnem[16] = { 0 };
int i = 0, j = 0;
const char *asm_str_buf = O->buffer;
// Skip spaces and tabs
while (asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t') {
if (!asm_str_buf[i]) {
MI->flat_insn->alias_id = -1;
return;
}
++i;
}
for (; j < sizeof(alias_mnem) - 1; ++j, ++i) {
if (!asm_str_buf[i] || asm_str_buf[i] == ' ' || asm_str_buf[i] == '\t')
break;
alias_mnem[j] = O->buffer[i];
}

MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);
}

31 changes: 30 additions & 1 deletion Mapping.h
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,9 @@ typedef struct insn_map {
[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
union {
ppc_suppl_info ppc;
} suppl_info; // Supplementary information for each instruction.
#endif
} insn_map;

Expand Down Expand Up @@ -166,7 +169,7 @@ DEFINE_get_arch_detail(tricore, TriCore);
static inline bool detail_is_set(const MCInst *MI)
{
assert(MI && MI->flat_insn);
return MI->flat_insn->detail != NULL;
return MI->flat_insn->detail != NULL && MI->csh->detail_opt & CS_OPT_ON;
}

static inline cs_detail *get_detail(const MCInst *MI)
Expand All @@ -175,4 +178,30 @@ static inline cs_detail *get_detail(const MCInst *MI)
return MI->flat_insn->detail;
}

static inline bool set_detail_ops(const MCInst *MI)
{
assert(MI && MI->flat_insn);
return MI->fillDetailOps;
}

/// Returns if the given instruction is an alias instruction.
#define RETURN_IF_INSN_IS_ALIAS(MI) \
do { \
if (MI->isAliasInstr) \
return; \
} while(0)

void map_set_fill_detail_ops(MCInst *MI, bool Val);

static inline bool map_fill_detail_ops(MCInst *MI) {
assert(MI);
return MI->fillDetailOps;
}

void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias);

bool map_use_alias_details(const MCInst *MI);

void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);

#endif // CS_MAPPING_H
32 changes: 32 additions & 0 deletions SStream.c
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,26 @@

void SStream_Init(SStream *ss)
{
assert(ss);
ss->index = 0;
ss->buffer[0] = '\0';
ss->is_closed = false;
}

/**
* Open the output stream. Every write attempt is accepted again.
*/
void SStream_Open(SStream *ss) {
assert(ss);
ss->is_closed = false;
}

/**
* Closes the output stream. Every write attempt is ignored.
*/
void SStream_Close(SStream *ss) {
assert(ss);
ss->is_closed = true;
}

/**
Expand All @@ -34,6 +52,7 @@ void SStream_Init(SStream *ss)
void SStream_concat0(SStream *ss, const char *s)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
if (s[0] == '\0')
return;
unsigned int len = (unsigned int) strlen(s);
Expand All @@ -50,6 +69,7 @@ void SStream_concat0(SStream *ss, const char *s)
void SStream_concat1(SStream *ss, const char c)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
if (c == '\0')
return;
ss->buffer[ss->index] = c;
Expand All @@ -64,6 +84,7 @@ void SStream_concat1(SStream *ss, const char c)
void SStream_concat(SStream *ss, const char *fmt, ...)
{
#ifndef CAPSTONE_DIET
SSTREAM_RETURN_IF_CLOSED(ss);
va_list ap;
int ret;

Expand All @@ -77,6 +98,7 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
// print number with prefix #
void printInt64Bang(SStream *O, int64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
Expand All @@ -95,6 +117,7 @@ void printInt64Bang(SStream *O, int64_t val)

void printUInt64Bang(SStream *O, uint64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
Expand All @@ -104,6 +127,7 @@ void printUInt64Bang(SStream *O, uint64_t val)
// print number
void printInt64(SStream *O, int64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
Expand All @@ -122,6 +146,7 @@ void printInt64(SStream *O, int64_t val)

void printUInt64(SStream *O, uint64_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, val);
else
Expand All @@ -131,6 +156,7 @@ void printUInt64(SStream *O, uint64_t val)
// print number in decimal mode
void printInt32BangDec(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0)
SStream_concat(O, "#%u", val);
else {
Expand All @@ -143,6 +169,7 @@ void printInt32BangDec(SStream *O, int32_t val)

void printInt32Bang(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
Expand All @@ -161,6 +188,7 @@ void printInt32Bang(SStream *O, int32_t val)

void printInt32(SStream *O, int32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val >= 0) {
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
Expand All @@ -179,6 +207,7 @@ void printInt32(SStream *O, int32_t val)

void printUInt32Bang(SStream *O, uint32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", val);
else
Expand All @@ -187,6 +216,7 @@ void printUInt32Bang(SStream *O, uint32_t val)

void printUInt32(SStream *O, uint32_t val)
{
SSTREAM_RETURN_IF_CLOSED(O);
if (val > HEX_THRESHOLD)
SStream_concat(O, "0x%x", val);
else
Expand All @@ -195,10 +225,12 @@ void printUInt32(SStream *O, uint32_t val)

void printFloat(SStream *O, float val)
{
SSTREAM_RETURN_IF_CLOSED(O);
SStream_concat(O, "%e", val);
}

void printFloatBang(SStream *O, float val)
{
SSTREAM_RETURN_IF_CLOSED(O);
SStream_concat(O, "#%e", val);
}
11 changes: 11 additions & 0 deletions SStream.h
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,21 @@
typedef struct SStream {
char buffer[512];
int index;
bool is_closed;
} SStream;

#define SSTREAM_RETURN_IF_CLOSED(OS) \
do { \
if (OS->is_closed) \
return; \
} while(0)

void SStream_Init(SStream *ss);

void SStream_Open(SStream *ss);

void SStream_Close(SStream *ss);

void SStream_concat(SStream *ss, const char *fmt, ...);

void SStream_concat0(SStream *ss, const char *s);
Expand Down
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