PowerPC: disassembly of instructions with OE flag set

[PeterMatula]

Some PowerPC instructions come in several flavours which are enabled by certain bits in the instruction encoding. For example, addX can set bit 21 (Overflow Enabled) and bit 31 (With CR Update). http://www.ds.ewi.tudelft.nl/vakken/in1006/instruction-set/add.html

For add r1, r2, r3 there are the following combinations (big endian) checked with IDA and ODA:

1. 7c 22 1a 14 -- add r1, r2, r3
2. 7c 22 1a 15 -- add. r1, r2, r3
3. 7c 22 1e 14 -- addo r1, r2, r3
4. 7c 22 1e 15 -- addo. r1, r2, r3

Capstone seems to handle variants 1. and 2. by setting update_cr0 member of cs_ppc. However, variants 3. and 4. fail to disassemble in both master and next branch. This seems like a well documented feature, so am I missing something, or is this simply unsupported at the moment (it is true that I was unable to find such instructions in any real-world PPC binaries I have).

[aquynh]

the latest code in "next" still does not handle the last 2 cases. feel free to update TD files in https://github.com/aquynh/capstone/tree/next/suite/synctools/tablegen/PPC to support these.

[aik]

sadly llvm still does not know those so simple update does not help :-/