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Stm32h573 addition #27

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2355021
Added stm32h573 support in Kconfig
lb-anssi May 22, 2025
9760e75
Added defconfig and dts for new board
lb-anssi May 23, 2025
1fc75ce
Removed syscfg
lb-anssi May 26, 2025
0da6242
Add stm32h5 kconfig
lb-anssi May 26, 2025
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7 changes: 7 additions & 0 deletions configs/stm32h573i_dk_defconfig
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# SPDX-FileCopyrightText: 2025 ANSSI
# SPDX-License-Identifier: Apache-2.0

CONFIG_ARCH_MCU_STM32H573=y
CONFIG_FPU_SOFTFP_ABI=y
CONFIG_DRV_STM32_LPUART=y
CONFIG_STANDALONE_MODE=y
287 changes: 287 additions & 0 deletions dts/examples/stm32h573i_dk.dts
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/*
* Copyright (c) 2025 ANSSI
*
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <st/h5/stm32h573.dtsi>
#include <dt-bindings/pinctrl/stm32-pinctrl.h>
#include <sentry.dtsi>

/{
chosen {
sentry,debug_stdout = <&lpuart1>;
outpost,i2c_port = <&i2c1>;
};

reserved-memory {
tasks_code: memory@0800a000 {
reg = <0x0800a000 0x200000>;
compatible = "outpost,memory-pool";
};
tasks_ram: memory@20008000 {
reg = <0x20008000 0x280000>;
compatible = "outpost,memory-pool";
};
/* Adding shm for task 1*/
shm_task1: memory@2000a000 {
reg = <0x2000a000 0x512>;
dma-pool; // DMA allowed from/to this SHM
outpost,shm;
outpost,no-map;
outpost,label = <0xf00>;// shm label, unique
outpost,owner = <0xc001f001>; // task label
};
/* Adding shm for task 2*/
shm_task2: memory@2000a200 {
reg = <0x2000a200 0x512>;
dma-pool; // DMA allowed from/to this SHM
outpost,shm;
outpost,no-map;
outpost,label = <0xf01>;// shm label, unique
outpost,owner = <0xc001f002>; // task label
};
};

aliases {
pll = &pll1;
};

led0: led_0 {
compatible = "gpio-leds";
status = "disabled";
};

led1: led_1 {
compatible = "gpio-leds";
status = "disabled";
};

led2: led_2 {
compatible = "gpio-leds";
status = "disabled";
};

backlight: backlight {
compatible = "gpio-leds";
status = "disabled";
};

panel: panel {
compatible = "gpio-leds";
status = "disabled";
};

touch: touch_1 {
compatible = "gpio";
status = "disabled";
};

sram1: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_M(1)>;
};

};

&flash0 {
reg = <0x08000000 DT_SIZE_M(4)>;
};

&clk_lsi {
status = "okay";
};

&clk_hsi {
status = "okay";
};

&clk_hse {
status = "okay";
};

&pll1 {
status = "okay";
};

&pll3 {
status = "okay";
};

&flash {
wait-state = <4>; /* According to voltage supply and sysclock */
status = "okay";
};

&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
bus-prescalers = <0>, <2>, <0>, <0>;
bus-names = "ahb", "apb1", "apb2", "apb3";
status = "okay";
};

&exti {
events = <26>;
status = "okay";
};

&gpioa {
status = "okay";
};

&gpiob {
status = "okay";
};

&gpioc {
status = "okay";
};

&gpiod {
status = "okay";
};

&gpioe {
status = "okay";
};

&gpiof {
status = "okay";
};

&gpiog {
status = "okay";
};

&lpuart1{
status = "okay";
pinctrl-0 = <&lpuart1_tx_pc1>, <&lpuart1_rx_pc0>;
};

&pinctrl {
lpuart1_tx_pc1: lpuart1_tx_pc1 {
label = "usart_tx";
pinmux = <&gpioc 1 STM32_DT_PIN_MODE_ALTFUNC(8)>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

lpuart1_rx_pc0: lpuart1_rx_pc0 {
label = "usart_rx";
pinmux = <&gpioc 0 STM32_DT_PIN_MODE_ALTFUNC(8)>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

i2c1_scl_pb8: i2c_scl_pb8 {
label = "scl";
pinmux = <&gpiob 8 STM32_DT_PIN_MODE_ALTFUNC(4)>;
pincfg = <STM32_OTYPER_OPEN_DRAIN \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_PULL_UP>;
};

i2c1_sda_pb9: i2c_sda_pb9 {
label = "sda";
pinmux = <&gpiob 9 STM32_DT_PIN_MODE_ALTFUNC(4)>;
pincfg = <STM32_OTYPER_OPEN_DRAIN \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_PULL_UP>;
};

panel_reset_pf3: panel_reset_pf3 {
label = "panel_rst";
pinmux = <&gpiof 3 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_LOW_SPEED \
STM32_PUPDR_PULL_DOWN>;
};

backlight_pa9: backlight_pa9 {
label = "backlight";
pinmux = <&gpioa 9 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_LOW_SPEED \
STM32_PUPDR_NO_PULL>;
};

touch_rstn: touch_rstn {
label = "touch_rst";
pinmux = <&gpiof 4 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_OPEN_DRAIN \
STM32_OSPEEDR_LOW_SPEED \
STM32_PUPDR_PULL_UP>;
};

touch_int_input: touch_int_input {
label = "touch_int_input";
pinmux = <&gpiof 5 STM32_DT_PIN_MODE_INPUT>;
pincfg = <STM32_OTYPER_OPEN_DRAIN \
STM32_OSPEEDR_LOW_SPEED \
STM32_PUPDR_PULL_UP>;
};

touch_int_output: touch_int_output {
label = "touch_int_output";
pinmux = <&gpiof 5 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_LOW_SPEED \
STM32_PUPDR_NO_PULL>;
};

led_pa5: led_pa5 {
pinmux = <&gpioa 5 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

led_pa6: led_pa6 {
pinmux = <&gpioa 6 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

led_pf7: led_pf7 {
pinmux = <&gpiof 7 STM32_DT_PIN_MODE_OUTPUT>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

spi3_miso_pc11: spi3_miso_pc11 {
pinmux = <&gpioc 11 STM32_DT_PIN_MODE_ALTFUNC(6)>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

spi3_mosi_pc12: spi3_mosi_pc12 {
pinmux = <&gpioc 12 STM32_DT_PIN_MODE_ALTFUNC(6)>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};
spi3_sclk_pc10: spi3_sclk_pc10 {
pinmux = <&gpioc 10 STM32_DT_PIN_MODE_ALTFUNC(6)>;
pincfg = <STM32_OTYPER_PUSH_PULL \
STM32_OSPEEDR_VERY_HIGH_SPEED \
STM32_PUPDR_NO_PULL>;
};

};

&rng {
status = "okay";
};

// &syscfg {
// status = "okay";
// };

19 changes: 19 additions & 0 deletions kernel/src/arch/asm-cortex-m/Kconfig
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Expand Up @@ -160,6 +160,20 @@ config SOC_SUBFAMILY_STM32U5
help
STM32U5 family is based on Cortex-M33 with FPU, PMSAv8 MPU and TrustZone

config SOC_SUBFAMILY_STM32H5
bool
select ARCH_ARM_CORTEX_M33
select SOC_FAMILY_STM32
select HAS_FPU
select HAS_FPU_FPV5
select HAS_TRUSTZONE
select HAS_DCACHE
select HAS_ICACHE
select HAS_RNG
select HAS_GPDMA
help
STM32U5 family is based on Cortex-M33 with FPU, PMSAv8 MPU and TrustZone

config SOC_SUBFAMILY_STM32WB
bool
select ARCH_ARM_CORTEX_M4
Expand Down Expand Up @@ -237,6 +251,7 @@ config ARCH_SOCNAME
default "STM32U5A9" if ARCH_MCU_STM32U5A9
default "STM32U5FX" if ARCH_MCU_STM32U5FX
default "STM32U5GX" if ARCH_MCU_STM32U5GX
default "STM32H573" if ARCH_MCU_STM32H573

# User-accessible selectors

Expand Down Expand Up @@ -284,6 +299,10 @@ config ARCH_MCU_STM32U5A9
bool "STM32U5A9"
select SOC_SUBFAMILY_STM32U59_Ax

config ARCH_MCU_STM32H573
bool "STM32H573"
select SOC_SUBFAMILY_STM32H5

endchoice

if HAS_FPU
Expand Down
3 changes: 2 additions & 1 deletion kernel/src/drivers/meson.build
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Expand Up @@ -25,7 +25,8 @@ if kconfig_data.get('CONFIG_HAS_RNG', 0) == 1
subdir('rng')
endif

subdir('syscfg')
# subdir('syscfg')

if kconfig_data.get('CONFIG_DEBUG_OUTPUT_USART', 0) == 1
subdir('usart')
endif
Expand Down
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