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Winch: implement v128 neg and shifts for x64 #10170

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Winch: implement v128 neg and shifts for x64 #10170

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45bca85
packed integer neg
MarinPostma Jan 29, 2025
1b69b27
v128 shifts
MarinPostma Feb 3, 2025
9f92a02
shift tests
MarinPostma Feb 3, 2025
e89fc86
fmt
MarinPostma Feb 3, 2025
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fmt
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@MarinPostma
MarinPostma committed Feb 3, 2025
commit e89fc86ea50ba3377b2f5d07413d01fc1a62ae4d
2 changes: 0 additions & 2 deletions crates/wast-util/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -449,8 +449,6 @@ impl WastTest {
"spec_testsuite/simd_i64x2_arith2.wast",
"spec_testsuite/simd_i64x2_extmul_i32x4.wast",
"spec_testsuite/simd_i8x16_arith2.wast",
"spec_testsuite/simd_i8x16_sat_arith.wast",
"spec_testsuite/simd_i8x16_cmp.wast",
"spec_testsuite/simd_int_to_int_extend.wast",
"spec_testsuite/simd_lane.wast",
"spec_testsuite/simd_load.wast",
Expand Down
7 changes: 6 additions & 1 deletion winch/codegen/src/isa/aarch64/masm.rs
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Expand Up @@ -1136,7 +1136,12 @@ impl Masm for MacroAssembler {
Err(anyhow!(CodeGenError::unimplemented_masm_instruction()))
}

fn v128_shift(&mut self, _context: &mut CodeGenContext<Emission>, _lane_width: OperandSize, _shift_kind: ShiftKind) -> Result<()> {
fn v128_shift(
&mut self,
_context: &mut CodeGenContext<Emission>,
_lane_width: OperandSize,
_shift_kind: ShiftKind,
) -> Result<()> {
Err(anyhow!(CodeGenError::unimplemented_masm_instruction()))
}
}
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2 changes: 1 addition & 1 deletion winch/codegen/src/isa/x64/address.rs
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Expand Up @@ -16,7 +16,7 @@ pub(crate) enum Address {
base: Reg,
index: Reg,
shift: u8,
}
},
}

impl Address {
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14 changes: 9 additions & 5 deletions winch/codegen/src/isa/x64/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,7 @@ use cranelift_codegen::{
},
},
settings, CallInfo, Final, MachBuffer, MachBufferFinalized, MachInstEmit, MachInstEmitState,
MachLabel, PatchRegion, RelocDistance, VCodeConstantData, VCodeConstants,
Writable,
MachLabel, PatchRegion, RelocDistance, VCodeConstantData, VCodeConstants, Writable,
};

use crate::reg::WritableReg;
Expand Down Expand Up @@ -1903,7 +1902,7 @@ impl Assembler {
let op = match size {
OperandSize::S32 => AvxOpcode::Vmovd,
OperandSize::S64 => AvxOpcode::Vmovq,
_ => unreachable!()
_ => unreachable!(),
};

self.emit(Inst::GprToXmmVex {
Expand All @@ -1912,7 +1911,6 @@ impl Assembler {
dst: dst.map(Into::into),
src_size: size.into(),
})

}

/// The `vpinsr` opcode to use.
Expand All @@ -1926,7 +1924,13 @@ impl Assembler {
}
}

pub fn xmm_vex_op_rr(&mut self, op: AvxOpcode, src1: Reg, src2: impl Into<XmmMemImm>, dst: WritableReg) {
pub fn xmm_rmi_rvex(
&mut self,
op: AvxOpcode,
src1: Reg,
src2: impl Into<XmmMemImm>,
dst: WritableReg,
) {
self.emit(Inst::XmmRmiRVex {
op,
src1: src1.into(),
Expand Down
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