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fixing 10G tcp & udp
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David Sidler committed Sep 8, 2019
1 parent 7c2dc62 commit 49548c2
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Showing 12 changed files with 174 additions and 111 deletions.
77 changes: 45 additions & 32 deletions hdl/common/tcp_stack.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,8 +122,11 @@ axis_meta #(.WIDTH(16)) axis_listen_port();
axis_meta #(.WIDTH(8)) axis_listen_port_status();
axis_meta #(.WIDTH(48)) axis_open_connection();
axis_meta #(.WIDTH(24)) axis_open_status();
axis_meta #(.WIDTH(16)) axis_close_connection();

axis_meta #(.WIDTH(88)) axis_notifications();
axis_meta #(.WIDTH(32)) axis_read_package();
axis_meta #(.WIDTH(16)) axis_rx_metadata();
axis_meta #(.WIDTH(32)) axis_tx_metadata();


Expand Down Expand Up @@ -269,9 +272,9 @@ toe_ip toe_inst (
.m_axis_listen_port_rsp_V_TDATA(axis_listen_port_status.data),

// notification & read request
.m_axis_notification_V_TVALID(m_axis_notifications.valid),
.m_axis_notification_V_TREADY(m_axis_notifications.ready),
.m_axis_notification_V_TDATA(m_axis_notifications.data),
.m_axis_notification_V_TVALID(axis_notifications.valid),
.m_axis_notification_V_TREADY(axis_notifications.ready),
.m_axis_notification_V_TDATA(axis_notifications.data),
.s_axis_rx_data_req_V_TVALID(axis_read_package.valid),
.s_axis_rx_data_req_V_TREADY(axis_read_package.ready),
.s_axis_rx_data_req_V_TDATA(axis_read_package.data),
Expand All @@ -283,14 +286,14 @@ toe_ip toe_inst (
.m_axis_open_conn_rsp_V_TVALID(axis_open_status.valid),
.m_axis_open_conn_rsp_V_TREADY(axis_open_status.ready),
.m_axis_open_conn_rsp_V_TDATA(axis_open_status.data),
.s_axis_close_conn_req_V_V_TVALID(s_axis_close_connection.valid),
.s_axis_close_conn_req_V_V_TREADY(s_axis_close_connection.ready),
.s_axis_close_conn_req_V_V_TDATA(s_axis_close_connection.data),
.s_axis_close_conn_req_V_V_TVALID(axis_close_connection.valid),
.s_axis_close_conn_req_V_V_TREADY(axis_close_connection.ready),
.s_axis_close_conn_req_V_V_TDATA(axis_close_connection.data),

// rx data
.m_axis_rx_data_rsp_metadata_V_V_TVALID(m_axis_rx_metadata.valid),
.m_axis_rx_data_rsp_metadata_V_V_TREADY(m_axis_rx_metadata.ready),
.m_axis_rx_data_rsp_metadata_V_V_TDATA(m_axis_rx_metadata.data),
.m_axis_rx_data_rsp_metadata_V_V_TVALID(axis_rx_metadata.valid),
.m_axis_rx_data_rsp_metadata_V_V_TREADY(axis_rx_metadata.ready),
.m_axis_rx_data_rsp_metadata_V_V_TDATA(axis_rx_metadata.data),
.m_axis_rx_data_rsp_TVALID(m_axis_rx_data.valid),
.m_axis_rx_data_rsp_TREADY(m_axis_rx_data.ready),
.m_axis_rx_data_rsp_TDATA(m_axis_rx_data.data),
Expand Down Expand Up @@ -685,7 +688,7 @@ end



// Register slices to avoid combinatorial loops created by HLS
// Register slices to avoid combinatorial loops created by HLS due to the new axis INTERFACE (enforced since 19.1)

axis_register_slice_16 listen_port_slice (
.aclk(net_clk), // input wire aclk
Expand Down Expand Up @@ -731,6 +734,28 @@ axis_register_slice_24 open_status_slice (
.m_axis_tdata(m_axis_open_status.data) // output wire [7 : 0] m_axis_tdata
);

axis_register_slice_16 close_connection_slice (
.aclk(net_clk), // input wire aclk
.aresetn(net_aresetn), // input wire aresetn
.s_axis_tvalid(s_axis_close_connection.valid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_close_connection.ready), // output wire s_axis_tready
.s_axis_tdata(s_axis_close_connection.data), // input wire [7 : 0] s_axis_tdata
.m_axis_tvalid(axis_close_connection.valid), // output wire m_axis_tvalid
.m_axis_tready(axis_close_connection.ready), // input wire m_axis_tready
.m_axis_tdata(axis_close_connection.data) // output wire [7 : 0] m_axis_tdata
);

axis_register_slice_88 notification_slice (
.aclk(net_clk), // input wire aclk
.aresetn(net_aresetn), // input wire aresetn
.s_axis_tvalid(axis_notifications.valid), // input wire s_axis_tvalid
.s_axis_tready(axis_notifications.ready), // output wire s_axis_tready
.s_axis_tdata(axis_notifications.data), // input wire [7 : 0] s_axis_tdata
.m_axis_tvalid(m_axis_notifications.valid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_notifications.ready), // input wire m_axis_tready
.m_axis_tdata(m_axis_notifications.data) // output wire [7 : 0] m_axis_tdata
);

axis_register_slice_32 read_package_slice (
.aclk(net_clk), // input wire aclk
.aresetn(net_aresetn), // input wire aresetn
Expand All @@ -742,6 +767,16 @@ axis_register_slice_32 read_package_slice (
.m_axis_tdata(axis_read_package.data) // output wire [7 : 0] m_axis_tdata
);

axis_register_slice_16 axis_rx_metadata_slice (
.aclk(net_clk), // input wire aclk
.aresetn(net_aresetn), // input wire aresetn
.s_axis_tvalid(axis_rx_metadata.valid), // input wire s_axis_tvalid
.s_axis_tready(axis_rx_metadata.ready), // output wire s_axis_tready
.s_axis_tdata(axis_rx_metadata.data), // input wire [7 : 0] s_axis_tdata
.m_axis_tvalid(m_axis_rx_metadata.valid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_rx_metadata.ready), // input wire m_axis_tready
.m_axis_tdata(m_axis_rx_metadata.data) // output wire [7 : 0] m_axis_tdata
);
axis_register_slice_32 axis_tx_metadata_slice (
.aclk(net_clk), // input wire aclk
.aresetn(net_aresetn), // input wire aresetn
Expand Down Expand Up @@ -771,28 +806,6 @@ always @(posedge net_clk) begin
end
end

/*ila_mixed tco_debug (
.clk(net_clk), // input wire clk
.probe0(s_axis_mem_read_data[ddrPortNetworkTx].valid), // input wire [0:0] probe0
.probe1(s_axis_mem_read_data[ddrPortNetworkTx].ready), // input wire [0:0] probe1
.probe2(m_axis_tx_data.valid), // input wire [0:0] probe2
.probe3(m_axis_tx_data.ready), // input wire [0:0] probe3
.probe4(m_axis_mem_read_cmd[ddrPortNetworkTx].valid), // input wire [0:0] probe4
.probe5(m_axis_mem_read_cmd[ddrPortNetworkTx].ready), // input wire [0:0] probe5
.probe6(m_axis_rx_metadata.valid), // input wire [0:0] probe6
.probe7(s_axis_mem_read_data[ddrPortNetworkTx].last), // input wire [0:0] probe7
.probe8(read_cmd_counter), // input wire [15:0] probe8
.probe9(read_pkg_counter), // input wire [15:0] probe9
.probe10(s_axis_mem_read_data[ddrPortNetworkTx].keep[31:16]), // input wire [15:0] probe10
.probe11(m_axis_mem_read_cmd[ddrPortNetworkTx].address[20:16]),// input wire [15:0] probe11
.probe12(s_axis_mem_read_data[ddrPortNetworkTx].keep[15:0]),
//.probe12({s_axis_tx_data.ready, s_axis_tx_data.valid, s_axis_tx_metadata.ready, s_axis_tx_metadata.valid, m_axis_open_status.ready, m_axis_open_status.valid, m_axis_rx_data.last, m_axis_rx_data.ready, m_axis_rx_data.valid, m_axis_rx_metadata.ready, m_axis_rx_metadata.valid, s_axis_read_package.ready, s_axis_read_package.valid, m_axis_notifications.ready, m_axis_notifications.valid, s_axis_rx_data.last, m_axis_tx_data.last}), // input wire [15:0] probe12
.probe13({m_axis_tx_data.last, m_axis_mem_write_data[ddrPortNetworkTx].last, m_axis_mem_write_data[ddrPortNetworkTx].ready, m_axis_mem_write_data[ddrPortNetworkTx].valid, s_axis_mem_read_sts[ddrPortNetworkTx].ready, s_axis_mem_read_sts[ddrPortNetworkTx].valid, s_axis_mem_write_sts[ddrPortNetworkTx].ready, s_axis_mem_write_sts[ddrPortNetworkTx].valid, axis_rxwrite_data.last, axis_rxwrite_data.ready, axis_rxwrite_data.valid, axis_rxread_data.last, axis_rxread_data.ready, axis_rxread_data.valid, m_axis_mem_write_cmd[ddrPortNetworkTx].ready, m_axis_mem_write_cmd[ddrPortNetworkTx].valid, m_axis_mem_read_cmd[ddrPortNetworkTx].ready, m_axis_mem_read_cmd[ddrPortNetworkTx].valid}), // input wire [15:0] probe13
.probe14(m_axis_mem_read_cmd[ddrPortNetworkTx].address[15:0]), // input wire [15:0] probe14
.probe15(m_axis_mem_read_cmd[ddrPortNetworkTx].length[15:0]) // input wire [15:0] probe15
);*/

end
else begin
assign s_axis_rx_data.ready = 1'b1;
Expand Down
76 changes: 64 additions & 12 deletions hdl/common/udp_stack.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,11 +54,16 @@ module udp_stack #(
generate
if (UDP_EN == 1) begin

axis_meta #(.WIDTH(48)) axis_ip_to_udp_slice_meta();
axis_meta #(.WIDTH(48)) axis_ip_to_udp_meta();
axis_meta #(.WIDTH(48)) axis_udp_to_ip_slice_meta();
axis_meta #(.WIDTH(48)) axis_udp_to_ip_meta();

axi_stream #(.WIDTH(WIDTH)) axis_ip_to_udp_data();
axi_stream #(.WIDTH(WIDTH)) axis_udp_to_ip_data();

axis_meta #(.WIDTH(176)) axis_udp_rx_metadata();
axis_meta #(.WIDTH(176)) axis_udp_tx_metadata();


ipv4_ip ipv4_inst (
Expand All @@ -70,9 +75,9 @@ ipv4_ip ipv4_inst (
.s_axis_rx_data_TDATA(s_axis_rx_data.data),
.s_axis_rx_data_TKEEP(s_axis_rx_data.keep),
.s_axis_rx_data_TLAST(s_axis_rx_data.last),
.m_axis_rx_meta_V_TVALID(axis_ip_to_udp_meta.valid),
.m_axis_rx_meta_V_TREADY(axis_ip_to_udp_meta.ready),
.m_axis_rx_meta_V_TDATA(axis_ip_to_udp_meta.data),
.m_axis_rx_meta_V_TVALID(axis_ip_to_udp_slice_meta.valid),
.m_axis_rx_meta_V_TREADY(axis_ip_to_udp_slice_meta.ready),
.m_axis_rx_meta_V_TDATA(axis_ip_to_udp_slice_meta.data),
.m_axis_rx_data_TVALID(axis_ip_to_udp_data.valid),
.m_axis_rx_data_TREADY(axis_ip_to_udp_data.ready),
.m_axis_rx_data_TDATA(axis_ip_to_udp_data.data),
Expand All @@ -96,6 +101,28 @@ ipv4_ip ipv4_inst (
.ap_clk(net_clk),
.ap_rst_n(net_aresetn)
);

axis_register_slice_48 rx_ip_meta_slice(
.aclk(net_clk),
.aresetn(net_aresetn),
.s_axis_tvalid(axis_ip_to_udp_slice_meta.valid),
.s_axis_tready(axis_ip_to_udp_slice_meta.ready),
.s_axis_tdata(axis_ip_to_udp_slice_meta.data),
.m_axis_tvalid(axis_ip_to_udp_meta.valid),
.m_axis_tready(axis_ip_to_udp_meta.ready),
.m_axis_tdata(axis_ip_to_udp_meta.data)
);
axis_register_slice_48 tx_ip_meta_slice(
.aclk(net_clk),
.aresetn(net_aresetn),
.s_axis_tvalid(axis_udp_to_ip_slice_meta.valid),
.s_axis_tready(axis_udp_to_ip_slice_meta.ready),
.s_axis_tdata(axis_udp_to_ip_slice_meta.data),
.m_axis_tvalid(axis_udp_to_ip_meta.valid),
.m_axis_tready(axis_udp_to_ip_meta.ready),
.m_axis_tdata(axis_udp_to_ip_meta.data)
);


udp_ip udp_inst (
.reg_listen_port_V(listen_port),
Expand All @@ -109,26 +136,26 @@ ipv4_ip ipv4_inst (
.s_axis_rx_data_TDATA(axis_ip_to_udp_data.data),
.s_axis_rx_data_TKEEP(axis_ip_to_udp_data.keep),
.s_axis_rx_data_TLAST(axis_ip_to_udp_data.last),
.m_axis_rx_meta_V_TVALID(m_axis_udp_rx_metadata.valid),
.m_axis_rx_meta_V_TREADY(m_axis_udp_rx_metadata.ready),
.m_axis_rx_meta_V_TDATA(m_axis_udp_rx_metadata.data),
.m_axis_rx_meta_V_TVALID(axis_udp_rx_metadata.valid),
.m_axis_rx_meta_V_TREADY(axis_udp_rx_metadata.ready),
.m_axis_rx_meta_V_TDATA(axis_udp_rx_metadata.data),
.m_axis_rx_data_TVALID(m_axis_udp_rx_data.valid),
.m_axis_rx_data_TREADY(m_axis_udp_rx_data.ready),
.m_axis_rx_data_TDATA(m_axis_udp_rx_data.data),
.m_axis_rx_data_TKEEP(m_axis_udp_rx_data.keep),
.m_axis_rx_data_TLAST(m_axis_udp_rx_data.last),
//TX
.s_axis_tx_meta_V_TVALID(s_axis_udp_tx_metadata.valid),
.s_axis_tx_meta_V_TREADY(s_axis_udp_tx_metadata.ready),
.s_axis_tx_meta_V_TDATA(s_axis_udp_tx_metadata.data),
.s_axis_tx_meta_V_TVALID(axis_udp_tx_metadata.valid),
.s_axis_tx_meta_V_TREADY(axis_udp_tx_metadata.ready),
.s_axis_tx_meta_V_TDATA(axis_udp_tx_metadata.data),
.s_axis_tx_data_TVALID(s_axis_udp_tx_data.valid),
.s_axis_tx_data_TREADY(s_axis_udp_tx_data.ready),
.s_axis_tx_data_TDATA(s_axis_udp_tx_data.data),
.s_axis_tx_data_TKEEP(s_axis_udp_tx_data.keep),
.s_axis_tx_data_TLAST(s_axis_udp_tx_data.last),
.m_axis_tx_meta_V_TVALID(axis_udp_to_ip_meta.valid),
.m_axis_tx_meta_V_TREADY(axis_udp_to_ip_meta.ready),
.m_axis_tx_meta_V_TDATA(axis_udp_to_ip_meta.data),
.m_axis_tx_meta_V_TVALID(axis_udp_to_ip_slice_meta.valid),
.m_axis_tx_meta_V_TREADY(axis_udp_to_ip_slice_meta.ready),
.m_axis_tx_meta_V_TDATA(axis_udp_to_ip_slice_meta.data),
.m_axis_tx_data_TVALID(axis_udp_to_ip_data.valid),
.m_axis_tx_data_TREADY(axis_udp_to_ip_data.ready),
.m_axis_tx_data_TDATA(axis_udp_to_ip_data.data),
Expand All @@ -138,6 +165,31 @@ ipv4_ip ipv4_inst (
.ap_clk(net_clk),
.ap_rst_n(net_aresetn)
);

// Register slices to avoid combinatorial loops created by HLS due to the new axis INTERFACE (enforced since 19.1)

axis_register_slice_176 rx_udp_meta_slice(
.aclk(net_clk),
.aresetn(net_aresetn),
.s_axis_tvalid(axis_udp_rx_metadata.valid),
.s_axis_tready(axis_udp_rx_metadata.ready),
.s_axis_tdata(axis_udp_rx_metadata.data),
.m_axis_tvalid(m_axis_udp_rx_metadata.valid),
.m_axis_tready(m_axis_udp_rx_metadata.ready),
.m_axis_tdata(m_axis_udp_rx_metadata.data)
);

axis_register_slice_176 tx_udp_meta_slice(
.aclk(net_clk),
.aresetn(net_aresetn),
.s_axis_tvalid(s_axis_udp_tx_metadata.valid),
.s_axis_tready(s_axis_udp_tx_metadata.ready),
.s_axis_tdata(s_axis_udp_tx_metadata.data),
.m_axis_tvalid(axis_udp_tx_metadata.valid),
.m_axis_tready(axis_udp_tx_metadata.ready),
.m_axis_tdata(axis_udp_tx_metadata.data)
);

end
else begin

Expand Down
4 changes: 2 additions & 2 deletions hls/hash_table/hash_table.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <math.h>

//Copied from hlslib by Johannes de Fine Licht https://github.com/definelicht/hlslib/blob/master/include/hlslib/xilinx/Utility.h
constexpr unsigned char ConstLog2(unsigned long val) {
return val == 0 ? 0 : 1 + ConstLog2(val >> 1);
constexpr unsigned long ConstLog2(unsigned long val) {
return val == 1 ? 0 : 1 + ConstLog2(val >> 1);
}

const uint32_t MAX_KEY_SIZE = 64;
Expand Down
2 changes: 1 addition & 1 deletion hls/ip_handler/ip_handler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -454,7 +454,7 @@ void ip_handler(hls::stream<net_axis<WIDTH> >& s_axis_raw,
#pragma HLS STREAM variable=ipDataCheckFifo depth=64 //8, must hold IP header for checksum checking, max. 15 x 32bit
#pragma HLS STREAM variable=ipDataDropFifo depth=2
#pragma HLS STREAM variable=ipDataCutFifo depth=2
#pragma HLS STREAM variable=udpDataFifo depth=1
#pragma HLS STREAM variable=udpDataFifo depth=2
#pragma HLS STREAM variable=iph_subSumsFifoOut depth=2
#pragma HLS STREAM variable=validChecksumFifo depth=4
#pragma HLS STREAM variable=validIpAddressFifo depth=32
Expand Down
10 changes: 9 additions & 1 deletion hls/toe/dummy_memory.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ class dummyMemory {
int readLen;
ap_uint<16> writeAddr; //<8>
ap_uint<16> writeId;
//ap_uint<16> writeLen;
ap_uint<16> writeLen;
std::map<ap_uint<16>, ap_uint<8>*> storage;
std::map<ap_uint<16>, ap_uint<8>*>::iterator readStorageIt;
std::map<ap_uint<16>, ap_uint<8>*>::iterator writeStorageIt;
Expand All @@ -71,6 +71,9 @@ void dummyMemory<WIDTH>::setWriteCmd(mmCmd cmd)
// writeAddr = cmd.saddr(7, 0);
writeAddr = cmd.saddr(15, 0);
writeId = cmd.saddr(31, 16);
uint16_t tempLen = (uint16_t) cmd.bbt(15, 0);
writeLen = (int) tempLen;
//std::cout << "WRITE command: " << std::hex << cmd.saddr(15, 0) << " " << std::dec << cmd.bbt << std::endl;
}

template <int WIDTH>
Expand Down Expand Up @@ -119,12 +122,17 @@ void dummyMemory<WIDTH>::writeWord(net_axis<WIDTH>& word)
{
(writeStorageIt->second)[writeAddr] = word.data((i*8)+7, i*8);
writeAddr++;
writeLen--;
}
else
{
break;
}
}
if (word.last)
{
assert(writeLen == 0);
}
}

template <int WIDTH>
Expand Down
47 changes: 25 additions & 22 deletions hls/toe/make.tcl.in
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,27 +8,29 @@ create_clock -period ${CLOCK_PERIOD} -name default
set_top ${PROJECT_NAME}_top

add_files ${CMAKE_CURRENT_SOURCE_DIR}/../axi_utils.cpp
add_files ${CMAKE_CURRENT_SOURCE_DIR}/ack_delay/ack_delay.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/close_timer/close_timer.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/event_engine/event_engine.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/port_table/port_table.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/probe_timer/probe_timer.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/retransmit_timer/retransmit_timer.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_app_if/rx_app_if.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_app_stream_if/rx_app_stream_if.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_engine/rx_engine.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_sar_table/rx_sar_table.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/session_lookup_controller/session_lookup_controller.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/state_table/state_table.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_if/tx_app_if.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_stream_if/tx_app_stream_if.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_engine/tx_engine.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_sar_table/tx_sar_table.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_interface/tx_app_interface.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/toe.cpp -cflags "-I${CMAKE_CURRENT_BINARY_DIR}"


#add_files -tb test_toe.cpp
add_files ${CMAKE_CURRENT_SOURCE_DIR}/ack_delay/ack_delay.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/close_timer/close_timer.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/event_engine/event_engine.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/port_table/port_table.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/probe_timer/probe_timer.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/retransmit_timer/retransmit_timer.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_app_if/rx_app_if.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_app_stream_if/rx_app_stream_if.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_engine/rx_engine.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/rx_sar_table/rx_sar_table.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/session_lookup_controller/session_lookup_controller.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/state_table/state_table.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_if/tx_app_if.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_stream_if/tx_app_stream_if.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_engine/tx_engine.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_sar_table/tx_sar_table.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/tx_app_interface/tx_app_interface.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"
add_files ${CMAKE_CURRENT_SOURCE_DIR}/toe.cpp -cflags "-std=c++11 -I${CMAKE_CURRENT_BINARY_DIR}"


add_files -tb ${CMAKE_CURRENT_SOURCE_DIR}/toe_tb.cpp

config_rtl -disable_start_propagation


#Check which command
Expand All @@ -37,7 +39,8 @@ set command [lindex $argv 2]
if {$command == "synthesis"} {
csynth_design
} elseif {$command == "csim"} {
csim_design
csim_design -clean -argv {0 ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/io_fin_5.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/rxOutput.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/txOutput.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/rx_io_fin_5.gold}
# csim_design -clean -argv {0 ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/mysyn2.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/rxOutput.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/txOutput.dat ${CMAKE_CURRENT_SOURCE_DIR}/testVectors/rx_io_fin_5.gold}
} elseif {$command == "ip"} {
export_design -format ip_catalog -ipname "toe" -display_name "10G TCP Offload Engine" -description "TCP Offload Engine supporting 10Gbps line rate, up to 10K concurrent sessions." -vendor "ethz.systems" -version "1.6"
} elseif {$command == "installip"} {
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