[H4] OLED power sequencing cannot be controlled #7

Review finding H4, recorded 2026-10-14 for bonanzaDisplay v3. Original classification: High — resolve or obtain panel approval.

Location: J1 pins 3/29; U4; U2/U3; RES

Current status: Deferred by owner on 2026-10-14; not fixed. The previous hardware worked without sequencing, and the owner chose to leave the present topology in place for now. No load switch has been added. Keep this open for a future decision; the original high-severity classification is historical and does not override that explicit deferral. Revisit if the exact module vendor requires sequencing or startup/shutdown testing reveals a problem.

Original observation: J1 VCC connects directly to incoming 12 V. The logic supplies are generated downstream by the buck and LDOs. U4's 33 nF soft-start capacitor implies roughly 4.8 ms nominal ramp time.

Why it matters: SSD1322 recommends logic power and reset before VCC, and VCC off before logic power. The current topology gives the panel high voltage before its logic supplies have risen, with no independent VCC control.

Recommended action: Check the exact OLED module's sequencing requirements. If it has no internal sequencing accommodation, add a controllable VCC switch and implement the required startup/shutdown sequence. A firmware delay alone cannot delay a directly connected 12 V rail.

Completion criteria:

• Revisit the sequencing decision if module requirements or observed behavior warrant it; document vendor confirmation, a deliberate acceptance, or an implemented/tested sequencing solution.

Evidence: SSD1322, p. 30