Initial commit porting to python3

.gitignore

@@ -1,2 +1,3 @@
+__pycache__
 *.vhd
 *.v

cordic/cordic_sim.py

@@ -25,7 +25,7 @@
 
 
 import math
-import pipelined_cordic
+from . import pipelined_cordic
 from myhdl import *
 
 import numpy as np
@@ -141,14 +141,14 @@ def test_cordic(n=None):
     pyplot.axhline(math.sqrt(0.5**2+0.5**2))
     pyplot.axhline(-math.sqrt(0.5**2+0.5**2))
 
-    print 'Average amplitude error:', np.average(np.sqrt(np.power(outvals[:,0], 2) + np.power(outvals[:,1], 2)) - (INTMAX-1))
+    print('Average amplitude error:', np.average(np.sqrt(np.power(outvals[:,0], 2) + np.power(outvals[:,1], 2)) - (INTMAX-1)))
 
     pyplot.subplot(413, title="phase error of CORDIC")
     pyplot.plot(phases, ((np.arctan2(outvals[:,1], outvals[:,0]) - phases + np.pi) % (2*np.pi) - np.pi), '.')
     pyplot.axhline(np.arctan2(math.sqrt(0.5**2+0.5**2), INTMAX-1), ls=':', label="Rect")
     pyplot.axhline(-np.arctan2(math.sqrt(0.5**2+0.5**2), INTMAX-1), ls=':')
 
-    print 'Average phase error:', np.average((np.arctan2(outvals[:,1], outvals[:,0]) - phases + np.pi) % (2*np.pi) - np.pi)
+    print('Average phase error:', np.average((np.arctan2(outvals[:,1], outvals[:,0]) - phases + np.pi) % (2*np.pi) - np.pi))
 
     pyplot.axhline(2*np.pi / PHASE_MAX / 2, ls='--', label="Phase")
     pyplot.axhline(-2*np.pi / PHASE_MAX / 2, ls='--')

cordic/pipelined_cordic.py

@@ -27,7 +27,7 @@
 import  math
 from myhdl import *
 
-
+@block
 def CordicPipeline(clock, phase, output_cos, output_sin, CORDIC_STAGES=None, LUT_DEPTH=5, NON_SATURATING=True, RENAME=True):
     """Implement a Cordic polar to rectangular transformation. The
     length of the vector is one unit. The bit depth and number of pipelineing
@@ -130,7 +130,7 @@ def generate_lut(depth, maximum, output_bits, Kscale):
 
             lut.append((c, s))
 
-        lut = zip(*lut)
+        lut = list(zip(*lut))
 
         return tuple(lut)
 
@@ -199,7 +199,7 @@ def _convert_phase(_phase):
 
     if RENAME:
         # Only has an effect if the hierarchy is extracted using toVHDL_kh.py currently
-        CordicPipeline.func_name = "CordicPipeline_%i_%i_%i_%i" % (PHASE_PRECISION, len(output_cos), LUT_DEPTH, CORDIC_STAGES)
+        CordicPipeline.__name__ = "CordicPipeline_%i_%i_%i_%i" % (PHASE_PRECISION, len(output_cos), LUT_DEPTH, CORDIC_STAGES)
 
     #: Extra precision for the phase register.
     if CORDIC_STAGES:

nco/nco.py

@@ -28,14 +28,15 @@
 sys.path.append('..')
 from myhdl import *
 
+@block
 def NCOCordic(clock, reset, phi_step, out_cos, out_sin, PHASE_PRECISION=None, DITHER=None, LUT_DEPTH=None, CORDIC_STAGES=None):
 
     if PHASE_PRECISION is None:
         # Infer a sensible precision based on out_cos bit depth (ie. +1)
         PHASE_PRECISION = len(out_cos) + 1
 
     # Calculate a name for the NCO
-    NCOCordic.func_name = "NCOCordic_%i_%i_%i_%i" % (PHASE_PRECISION, len(out_cos), LUT_DEPTH if LUT_DEPTH else 0, CORDIC_STAGES if CORDIC_STAGES else 0)
+    NCOCordic.__name__ = "NCOCordic_%i_%i_%i_%i" % (PHASE_PRECISION, len(out_cos), LUT_DEPTH if LUT_DEPTH else 0, CORDIC_STAGES if CORDIC_STAGES else 0)
 
     instances = []
 
@@ -93,7 +94,7 @@ def passtrough():
     try:
         from toVHDL_kh import toVHDL_kh as toVHDL
     except:
-        print "Not keeping hierarchy as toVHDL_kh could not be imported!"
+        print("Not keeping hierarchy as toVHDL_kh could not be imported!")
 
     toVHDL(NCOCordic, clock, reset, phi_step, cos_out, sin_out, LUT_DEPTH=10, DITHER=3)
 

nco/parameterize_nco.py

@@ -50,7 +50,7 @@ def format_num(num):
         (-15, "f"),
         (-12, "p"),
         (-9, "n"),
-        (-6, u"µ"),
+        (-6, "µ"),
         (-3, "m"),
         (0, ""),
         (3, "k"),
@@ -137,9 +137,9 @@ def ensure_valid(self):
     def update_labels(self):
         self.labels['latency'].set_text('%i' % self.pipeline_length)
 
-        self.labels['phase_frequency'].set_text(u'𝚫 %sHz (%i)' % (format_num(1000*1000*(self.actual_tone - self.tone)), self.phase_step))
+        self.labels['phase_frequency'].set_text('𝚫 %sHz (%i)' % (format_num(1000*1000*(self.actual_tone - self.tone)), self.phase_step))
 
-        self.labels['frequency_resolution'].set_text(u'%sHz (%sHz)' % (format_num(1e6 * self.frequency / (2**self.phase_acc_bits)), format_num(1e6 * self.frequency / (2**self.phase_bits))))
+        self.labels['frequency_resolution'].set_text('%sHz (%sHz)' % (format_num(1e6 * self.frequency / (2**self.phase_acc_bits)), format_num(1e6 * self.frequency / (2**self.phase_bits))))
 
     def update_adjustments(self):
         assert self._adjustments is not None
@@ -546,18 +546,20 @@ def get_hwgen_args(self):
     def generate_vhdl(self, *args):
         func, args, kwargs = self.get_hwgen_args()
 
-        try:
-            from toVHDL_kh import toVHDL_kh as toVHDL
-        except:
-            print "Not keeping hierarchy as toVHDL_kh could not be imported!"
-            toVHDL = myhdl.toVHDL
+#        try:
+#            from toVHDL_kh import toVHDL_kh as toVHDL
+#        except:
+#            print("Not keeping hierarchy as toVHDL_kh could not be imported!")
+#            toVHDL = myhdl.toVHDL
 
-        toVHDL(func, *args, **kwargs)
+        inst = func(*args, **kwargs)
+        inst.convert(hdl='VHDL')
 
     def generate_verilog(self, *args):
         func, args, kwargs = self.get_hwgen_args()
 
-        myhdl.toVerilog(func, *args, **kwargs)
+        inst = func(*args, **kwargs)
+        inst.convert(hdl='Verilog')
 
     def quit(self, *args):
         self.simulate.cancel()

prng/rule30.py

@@ -26,6 +26,7 @@
 
 from myhdl import *
 
+@block
 def Rule30(clock, reset, rout, INITIAL_STATE=[1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, 0, 0], UPDATE_RULE=[0,1,1,1,1,0,0,0]):
 
     INITIAL_STATE = tuple(INITIAL_STATE)
@@ -68,6 +69,6 @@ def output():
     reset = ResetSignal(bool(True), True, True)
     rout = Signal(intbv(0)[3:])
 
-    #toVerilog(Rule30, reset, clock, rout)
-    toVHDL(Rule30, clock, reset, rout)
+    inst = Rule30(clock, reset, rout)
+    inst.convert(hdl='VHDL')
 

prng/rule30_reference.py

@@ -63,7 +63,7 @@ def __init__(self, rule, init_state):
 
     def print_state(self):
         """Print the current state of the cellular automata."""
-        print self.state
+        print(self.state)
 
 
     def update_state(self):

prng/rule30_test.py

@@ -44,7 +44,7 @@ def test_rule30():
 
     dut = rule30.Rule30(clock, reset, state, INITIAL_STATE, UPDATE_RULE)
 
-    @myhdl.always(myhdl.delay(10 / 2))
+    @myhdl.always(myhdl.delay(10 // 2))
     def advance_clock():
         clock.next = not clock
 
@@ -74,5 +74,5 @@ def check_equality():
 
 s.run(None)
 
-print "Everything seems good!"
+print("Everything seems good!")