Initial commit of the thesis source.

README.md

@@ -1,2 +1,4 @@
 # PhD-Thesis
-This is the public repository of my Ph.D. thesis.
+This is the public repository of my Ph.D. thesis, including the presentation from my defense. 
+
+The compiled version of my thesis is available on www.fit.cvut.cz/sites/default/files/PhDThesis-Benacek.pdf

defense-presentation/Makefile

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+# Configuration ###########################################
+# FILE = file name without tex
+# PDBFR = pdf browser
+# BIBTEX = bibtex command
+# LATEX = latex command to run
+FILE=prezentace
+PDFBR=qpdfview
+BIBTEX=bibtex
+LATEX=pdflatex -interaction=errorstopmode -shell-escape
+EDITOR=texstudio
+
+# Helping variables #######################################
+# Find all SVG figures
+DIA_TO_EPS := $(shell find ./pic -name "*.dia" | sed 's/\.dia/\.eps/g' | xargs)
+SVG_TO_EPS := $(shell find ./pic -name "*.svg" | sed 's/\.svg/\.eps/g'| xargs)
+PDF_FILES_TO_DELETE := $(shell find ./pic -name "*-converted-to.pdf" | xargs)
+
+# Makefile targets ########################################
+all: pdf 
+	make pdf
+
+open: all
+	$(PDFBR) $(FILE).pdf 1>/dev/null 2>/dev/null&
+
+pdf: figures
+	$(LATEX)  $(FILE).tex
+	if [ -f $(FILE).aux ]; then \
+		$(BIBTEX) $(FILE); \
+		$(LATEX)  $(FILE).tex; \
+		$(LATEX)  $(FILE).tex; \
+	fi
+
+texstudio:
+	$(EDITOR) prezentace.txss 1>/dev/null 2>/dev/null&
+
+clean:	
+	#Clean main directory
+	rm -rf *.lot *.ps *.log *.aux *.dvi *.nav *.out *.snm *.toc *.bbl *.blg *.lof *.acn *.ist *.loa *.vrb
+
+mrproper: clean	
+ifneq ($(strip $(PDF_FILES_TO_DELETE)),)
+	rm $(PDF_FILES_TO_DELETE)
+endif
+ifneq ($(strip $(SVG_TO_EPS)),)
+	rm $(SVG_TO_EPS)
+endif
+ifneq ($(strip $(DIA_TO_EPS)),)
+	rm $(DIA_TO_EPS)
+endif
+	rm $(FILE).pdf
+
+figures: $(SVG_TO_EPS) $(DIA_TO_EPS) 
+	@echo "All figures are converted"
+
+pic/%.eps: pic/%.dia
+	dia -t eps -e $@ $< 	
+
+pic/%.eps: pic/%.svg
+	inkscape -D -E $@ $<

defense-presentation/conclusion.tex

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+\section{Conclusion and Contributions}
+\subsection*{Conclusion and Contributions}
+\begin{frame}
+    \frametitle{Conclusion and Contributions}
+    \begin{itemize}
+        \fitem \textbf{My research is focused on mapping of abstract description to VHDL model of high-speed network device}
+        \fitem I provided the following:
+        %
+        \begin{enumerate}
+            \fitem Modular architecture of high-speed network device (\textbf{100\,Gbps} and beyond)
+            \fitem Process of mapping from \textbf{P4 language} (introduced in 2013) to the architecture of high-speed network device
+            \fitem Tool --- for verification of architecture and mapping process
+            \fitem Overview of usage of High Level Synthesis (C/C++) in high throughput designs. 
+            Results of this research were used in other research projects. 
+        \end{enumerate}
+        %
+        \fitem The quality of generated code is comparable to hand-written one
+        \begin{itemize}
+            \fitem More resources are the cost for flexibility
+        \end{itemize}
+        \fitem The result of this research was verified against real network test devices
+    \end{itemize}
+\end{frame}
+
+\subsection*{Publications and Evaluation Activities}
+\begin{frame}[allowframebreaks]
+    \frametitle{Publications and Evaluation Activities}
+    %
+    {
+    % Use the small font in all publications
+    \footnotesize
+    \textbf{\underline{Reviewed Publications of the Author Relevant to the Thesis}}
+    \begin{itemize}
+        \fitem[$\rightarrow$] \textbf{[FCCM16]} P. Ben\'{a}\v{c}ek, V. Pu\v{s} and H. Kub\'{a}tov\'{a}.
+        \textit{P4-to-VHDL: Automatic Generation of 100Gbps Packet Parsers}. IEEE 24\textsuperscript{th} Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM2016), Washington D.C., USA, 2016.
+        %
+        \fitem[$\rightarrow$] \textbf{[H2RC15]} P. Ben\'{a}\v{c}ek, V. Pu\v{s} and H. Kub\'{a}tov\'{a}. \textit{Automatic Generation of 100 Gbps Packet Parsers from P4 Description}.
+        First International Workshop on Heterogeneous High-performance Reconfigurable Computing, Austin, TX, USA, 2015.
+        %
+        \fitem[$\rightarrow$] \textbf{[DSD14]} P. Ben\'{a}\v{c}ek, H. Kub\'{a}tov\'{a} and V. Pu\v{s}. \textit{Architecture of Effective High-Speed Network Stream Merger}.
+        Digital System Design (DSD), 17\textsuperscript{th} Euromicro Conference on Digital System Design, pp. 459--464, Verona, Italy, 2014.
+        %
+        \fitem[$\rightarrow$] \textbf{[FPGA14]} P. Ben{\'a}{\v{c}}ek and V. Pu{\v{s}}.
+        \textit{Application specific processor with high-level synthesized instructions}.
+        ACM/SIGDA international symposium on Field-Programmable Gate Arrays, pp. 246--246, Monterey, CA, USA,
+        2014.
+        %
+        \fitem[$\rightarrow$] \textbf{[ANCS14]} P. Ben\'{a}\v{c}ek, T. \v{C}ejka, H. Kub\'{a}tov\'{a} and R. Bla\v{z}ek.
+        \textit{Change-Point Detection Method on 100 Gb/s Ethernet Interface}.
+        ACM/IEEE Symposium on Architectures for Networking and Communications Systems, Marina del Rey, CA, USA,
+        2014.
+        \smallskip \\ The paper has been cited in:
+        \begin{itemize}
+            \footnotesize
+            \fitem Nakamura, Kohei, Ami Hayashi, and Hiroki Matsutani. \textit{An FPGA-Based Low-Latency Network Processing for Spark Streaming}. Proceedings of the Workshop on Real-Time and Stream Analytics in Big Data (IEEE BigData 2016 Workshop), 2016.
+        \end{itemize}
+        %
+        \fitem[$\rightarrow$] \textbf{[MEMICS14]} P. Ben\'{a}\v{c}ek, T. \v{C}ejka, H. Kub\'{a}tov\'{a}, L. Kekely and R. Bla\v{z}ek.
+        \textit{FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks}.
+        Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Tel\v{c}, Czech Republic,
+        2014.
+        %
+        \fitem[$\rightarrow$] \textbf{[H2RC16]} P. Ben\'{a}\v{c}ek, V. Pu\v{s} and P. Ka\v{s}tovsk\'y.
+        \textit{P4-to-FPGA: High Performance Reconfigurable Networking (poster)}.
+        Second International Workshop on Heterogeneous High-performance Reconfigurable Computing, Salt Lake City, UT, USA,
+        2016.
+        %        
+        \fitem[$\rightarrow$] \textbf{[P4ST16]} P. Ben{\'a}{\v{c}}ek and V. Pu{\v{s}}.
+        \textit{P4-to-VHDL: Generating High Speed Network Devices (poster)}. 
+        P4 Workshop, Stanford, California, USA, 
+        2016.
+        %
+        \fitem[$\rightarrow$] \textbf{[FPL13]} L. Kekely, V. Pu\v{s}, P. Ben{\'a}\v{c}ek and J. Ko\v{r}enek.
+        textit{Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring}.
+        Field Programmable Logic and Applications (FPL), 24\textsuperscript{th} International Conference, pp. 1--4, Munich, Germany,
+        2014.
+        \smallskip \\ \smallskip The paper has been cited in:
+        \begin{itemize}
+            \footnotesize
+            \item D. Grochol, L. Sekanina, M. \v{Z}\'{a}dn\'{i}k, J. Ko\v{r}enek. \textit{Evolutionary circuit design for fast FPGA-based classification of network application protocols}. 
+            Applied Soft Computing, Volume 38, January 2016, pp. 933-941.
+            \item L. Tang, J. Yan, Z. Sun, T. Li, M. Zhang. \textit{Towards high-performance packet processing on commodity multi-cores: current issues and future directions}.
+            Research Paper Special Focus On Future Internet Architecture And Protocol Science China Information Sciences, December 2015, Volume 58, Issue 12, pp. 1-16.
+        \end{itemize}
+    \end{itemize}
+    %
+    \textbf{\underline{Submitted Publications}}
+    \begin{itemize}
+        \fitem[$\rightarrow$] \textbf{[MICPRO16]} P. Ben\'{a}\v{c}ek, H. Kub\'{a}tov\'{a} and V. Pu\v{s}.
+        \textit{P4-to-VHDL: Automatic Generation of High-Speed Input and Output Network Blocks}.
+        Microprocessors and Microsystems, Elsevier Journal, 2016.
+    \end{itemize}
+    %
+    \textbf{\underline{Evaluation Activities}}
+    \begin{itemize}
+      \fitem[$\rightarrow$] Review of article for the \textit{Journal of Parallel and Distributed Computing}. Article in journal, ISSN 0743-7315, 2016.
+      %
+      \fitem[$\rightarrow$] Conference Programme Committee member in the \textit{Track on Reconfigurable Computing for Networks and Communications}. International Conference on Reconfigurable Computing and FPGAs (ReConFig'2016), Cancun, Mexico, 2016.
+    \end{itemize}
+    %
+    \textbf{\underline{P4 Popularization}}
+    \begin{itemize}
+        \fitem[$\rightarrow$] \textbf{[ROOT16]} P. Ben{\'a}{\v{c}}ek and V. Pu{\v{s}} 
+        \textit{The P4 Language as the Future of SDN (CZ)}. 
+        root.cz (part 1 and part 2), 2016.
+        %
+        \fitem[$\rightarrow$] \textbf{[P4CES16]} P. Ben{\'a}{\v{c}}ek and V. Pu{\v{s}} 
+        \textit{The P4 Language as the Future of SDN (CZ)}. 
+        CESNET blog, 2016 
+
+     \end{itemize}
+    } 
+\end{frame}

defense-presentation/motivation.tex

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+\section{Motivation}
+\subsection*{Contributions}
+\begin{frame}
+    \frametitle{Contributions}
+    \begin{itemize}
+        \fitem \textbf{Keywords}: FPGA, P4, Mapping to VHDL model, 100\,Gbps
+        \fitem \textbf{My research is focused on mapping of abstract description to VHDL model of high-speed network device}
+        \fitem I provided the following:
+        %
+        \begin{enumerate}
+            \fitem Modular architecture of high-speed network device (\textbf{100\,Gbps} and beyond)
+            \fitem Process of mapping from \textbf{P4 language} (introduced in 2013) to the architecture of high-speed network device
+            \fitem Tool --- for verification of architecture and mapping process
+            \fitem Overview of usage of High Level Synthesis (C/C++) in high throughput designs. 
+            Results of this research were used in other research projects
+        \end{enumerate}
+    \end{itemize}
+    \begin{block}{Contribution to the current state-of-the-art}
+        I provided higher degree of flexibility to generation of FPGA based network devices from abstract description (P4 language).
+    \end{block}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Motivation}
+    \begin{itemize}
+        \fitem Network devices with fixed functionality are not sufficient
+        \fitem SDN (Software Defined-Networking)
+        \begin{itemize}
+            \fitem Promises higher degree of flexibility 
+            \fitem Two components --- SDN Controller and SDN Datapath
+            \fitem ($\bm{+}$) Application is implemented in controller
+            \fitem ($\bm{+}$) Datapath is reconfigurable 
+            \fitem ($\bm{-}$) HW devices support a limited set of protocols and actions
+        \end{itemize}
+
+        \fitem Current requirements on modern network devices
+        \begin{itemize}
+            \fitem Easy extensibility with new protocols and actions
+            \fitem Capability to process data at high rates (100\,Gbps and beyond)
+        \end{itemize}
+
+        \fitem \textit{Field Programmable Gate Array} (FPGA) provides a reprogrammable structure $\rightarrow$ suitable as a target technology 
+        \begin{itemize}
+            \fitem Programmed in Hardware Description Language (HDL)
+            \fitem Hard to learn
+        \end{itemize}
+    \end{itemize}
+\end{frame}

defense-presentation/operations-and-languages.tex

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+\section{Background}
+\subsection*{Fundamental Network Operations}
+\begin{frame} %[allowframebreaks]
+    \frametitle{Fundamental Network Operations}
+    \begin{itemize}
+       \fitem Fundamental network operations from the packet processing point of view
+       \begin{enumerate}
+           \fitem \textbf{Data Extraction} --- extraction of interesting data (i.e, protocol headers) from incoming packets
+           \fitem \textbf{Classification} --- categorization of incoming packets into classes (based on extracted data)
+           \fitem \textbf{Data Processing} --- perform an operation based on the assigned class (e.g., data modification, filtering, and so on)
+        \end{enumerate}
+
+        \fitem These network operations are the core of each network device
+        \fitem Each operation has an influence on throughput        
+    \end{itemize}
+\end{frame}
+
+\subsection*{Languages and Abstractions}
+\begin{frame}[allowframebreaks]
+    \frametitle{Languages and Packet Processing Abstractions}
+    \begin{itemize}
+        \fitem Current HLS tools - not suitable for describing high-speed network devices 
+        \begin{itemize}
+            \fitem The result highly depends on provided description 
+            \fitem Not suitable for novices
+        \end{itemize}
+        %
+        \fitem This drives researchers to provide domain specific languages which are suitable for computer networks 
+        \fitem Such languages typically describe packet processing using the match and action model
+        \begin{enumerate}
+            \fitem \textbf{Gorilla}
+            \begin{itemize}
+                \fitem Lavasani et al. introduce the language and translation to Verilog
+                \fitem Capable to hit 100\,Gbps 
+                \fitem Uses templates of processing engines and packet parsers $\rightarrow$ makes the approach somewhat static 
+                \fitem e.g., you have to implement the protocol parser if you want to support it
+            \end{itemize}
+
+            \pagebreak
+
+            \fitem \textbf{SDNet}
+            \begin{itemize}
+                \fitem Commercial solution from Xilinx
+                \fitem Introduces the PX language and translation to Verilog
+                \fitem Flexible solution capable to scale from 1 to 100\,Gpbs
+                \fitem Closed system $\rightarrow$ harder implementation of novel packet processing approaches 
+                (not suitable for researchers)
+            \end{itemize}
+
+            % Put the P4 to the next slide
+            \fitem \textbf{P4} (Programming Protocol-independent Packet Processors)
+            \begin{itemize}
+                \fitem High-level and platform-agnostic language which is developed since 2013
+                \fitem Provides a way to define a packet processing functionality
+                \fitem Designed to be platform independent (CPU, NPU, ASIC, FPGA)
+            \end{itemize}
+
+        \end{enumerate}
+    \end{itemize}
+\end{frame}
+
+\subsection*{Specification of P4 Language}
+\begin{frame}
+    \frametitle{P4} 
+    \framesubtitle{Popularized in  [P4CES16], [ROOT16]}
+    \begin{itemize} 
+        \fitem Relatively simple syntax\footnote{Specification of the language is available at \url{www.p4.org}}
+        \fitem The language defines five basic aspects of packet processing:
+        \begin{enumerate}
+            \fitem \textbf{Header Format} --- defines the structure of protocol
+            \fitem \textbf{Packet Parser} --- defines the process of header parsing
+            \fitem \textbf{Table Specification} --- defines how extracted fields are mapped to actions
+            \fitem \textbf{Action Specification} --- defines compound actions that may be executed for packets
+            \fitem \textbf{Control Program} --- defines the control flow among the tables
+        \end{enumerate} 
+        \fitem Front end of the compiler is available under open source license 
+        $\rightarrow$ compilers for different targets can be implemented      
+        \fitem The next step in the SDN ecosystem $\rightarrow$ provides a way for the specification
+        of SDN Datapath functionality
+    \end{itemize}
+\end{frame}
+
+\subsection*{Example}
+\begin{frame}[fragile,allowframebreaks]
+    \frametitle{Example of P4 Program}
+    \framesubtitle{Simple VLAN Tagging Device}
+    % Include the file with example
+    \input{p4-src}
+\end{frame}