PS/2 Mouse Driver (VHDL)

This project implements a PS/2 mouse driver using VHDL, developed as part of the Integrated Systems Design II course at PUCRS.

The design focuses on reading PS/2 protocol data from a mouse, decoding button states, X/Y movement, sign, overflow, and parity errors, using a finite state machine (FSM) architecture.

For verification details, testing notes, and technical explanations, refer to the project report*

Features

• Reads 33-bit PS/2 frames (start, data, parity, stop bits)
• Detects:
  • Left/right button press (LR)
  • X and Y movement, including negative direction (XS, YS)
  • Overflow conditions (XV, YV)
  • Parity errors (with frame discard and recovery mechanism)
• Provides 8-bit parallel X and Y output (X, Y) with an enable signal

Tools & Workflow

• Language: VHDL (hierarchical design)
• Simulation: ModelSim
• Synthesis & Analysis: Cadence Genus (timing, area, power reports)
• Clock domains:
  • Master clock (clock_in) at 100 MHz
  • PS/2 clock (ps2_clock) up to 30 kHz

File Overview

• ps2_driver.vhd: Main VHDL implementation
• tb_ps2_driver.vhd: Testbench for simulation and validation
• constraints.sdc: Synthesis constraints
• Timing, area, and power reports (available in /reports folder)

Project Context

This work was developed for academic purposes to explore:

• Digital logic design (combinational and sequential circuits)
• Communication protocols
• Finite state machine modeling
• Hardware synthesis and performance analysis

Notes

Parity error handling was designed to improve robustness: frames with parity inconsistencies are discarded, and the system waits before accepting new data, avoiding false reads from corrupted transmissions.