updated readme to reflect actual project

Caskman · Caskman · commit a8912d9767ce · 2013-09-26T21:01:22.000-07:00
diff --git a/readme.txt b/readme.txt
@@ -1,2 +1,6 @@
-pipelined datapath with forwarding, hazard detection, and two-way adaptive branch prediction
-tested on sll, add, and branching mainly
+
+ECE 369 Project
+
+Building a single stage MIPS processor in Verilog.  THEN upgrading it to a pipelined processor with zero synthesization success.
+
+
