GitHub - avirajs/MIPS-Processor-in-Verilog at a8912d9767cee2c49a88f66b8252d33af30176f8

Name		Name	Last commit message	Last commit date
Latest commit History 117 Commits
.gitattributes		.gitattributes
.gitignore		.gitignore
ALU32Bit.v		ALU32Bit.v
BranchPredictor.v		BranchPredictor.v
Controller.v		Controller.v
Controller_tb.v		Controller_tb.v
DataMemory.v		DataMemory.v
EX_MEM_Reg.v		EX_MEM_Reg.v
ForwardingControl.v		ForwardingControl.v
HazardDetector.v		HazardDetector.v
ID_EX_REG.v		ID_EX_REG.v
InstructionFetchUnit.v		InstructionFetchUnit.v
InstructionMemory.v		InstructionMemory.v
MEM_WB_REG.v		MEM_WB_REG.v
PCAdder.v		PCAdder.v
ProgramCounter.v		ProgramCounter.v
RegisterFile.v		RegisterFile.v
code.txt		code.txt
if_id_reg.v		if_id_reg.v
mux_16to1_32bit.v		mux_16to1_32bit.v
mux_2to1_1bit.v		mux_2to1_1bit.v
mux_2to1_32bit.v		mux_2to1_32bit.v
mux_2to1_5bit.v		mux_2to1_5bit.v
mux_4to1_32bit.v		mux_4to1_32bit.v
mux_4to1_5bit.v		mux_4to1_5bit.v
mux_8to1_32bit.v		mux_8to1_32bit.v
readme.txt		readme.txt
sign_extension.v		sign_extension.v
test_code.s		test_code.s
test_data.txt		test_data.txt

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ECE 369 Project

Building a single stage MIPS processor in Verilog.  THEN upgrading it to a pipelined processor with zero synthesization success.

Processor repo

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