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2efe73c
Merge thumbv6m and thumbv7em clock modules
ianrrees Jul 21, 2025
6c2a9bc
TODO Hack to compile, nightly only
ianrrees Jul 22, 2025
ceb1aca
Work towards clock v2 GCLK and PCLK for thumbv6
bradleyharden Dec 28, 2022
8a00b08
TODO Another hack to compile
ianrrees Jul 22, 2025
1be5a79
stash 2 xosc32k
ianrrees Jul 22, 2025
ddfae16
stash 2 xosc
ianrrees Jul 22, 2025
c38433a
stash 2 osculp32k
ianrrees Jul 22, 2025
7c95319
stash 2 reset
ianrrees Jul 22, 2025
06a42e0
TODO squash warnings
ianrrees Jul 22, 2025
ed91b5e
stash 2 pclk
ianrrees Jul 22, 2025
fab2ae5
stash 2 gclk
ianrrees Jul 22, 2025
fef6c2b
stash 2 dpll
ianrrees Jul 22, 2025
374a52a
stash 2 dfll
ianrrees Jul 22, 2025
8cf2229
Only enable RTC for D5x
ianrrees Jul 22, 2025
33dc482
WIP stash 2 enable v2 for thumbv6m
ianrrees Jul 22, 2025
3b5fcc1
stash 3 ahb
ianrrees Jul 22, 2025
a12a72a
Rename Pac -> Pac0
ianrrees Jul 23, 2025
81ebcfe
stash 3 pclk
ianrrees Jul 23, 2025
5d00b3d
stash 3 dpll
ianrrees Jul 22, 2025
341452a
TODO Hacky disable of DPLL DCO for thumbv6m
ianrrees Jul 23, 2025
3546f63
stash 3 apb - needs types first
ianrrees Jul 23, 2025
e048b05
More work on ahb
ianrrees Jul 23, 2025
85ae750
stash 3 types
ianrrees Jul 23, 2025
982eb40
stash 3 pclk
ianrrees Jul 23, 2025
21f11da
stash 3 apb
ianrrees Jul 23, 2025
1a36bfb
stash 4 reset. TODO: Remove thumbv6 from v7 file
ianrrees Jul 23, 2025
e025f40
TODO notes
ianrrees Jul 24, 2025
e3f08ed
stash 4 APB startup state using macro
ianrrees Jul 24, 2025
054d56e
Fixes in APB for D11/D21
ianrrees Jul 24, 2025
88230b1
partial! stash 4 - gclk
ianrrees Jul 25, 2025
bfa22dd
Remove with_gclk_max_expr!()
ianrrees Jul 25, 2025
3d3ca3d
stash 5 - osc
ianrrees Jul 24, 2025
9c55928
osc fixes and partial stash 5 - reset
ianrrees Jul 25, 2025
915b398
stash 4 - dfll
ianrrees Jul 25, 2025
7f985fb
fixup gclk
ianrrees Jul 26, 2025
5033501
stash 4 - types
ianrrees Jul 26, 2025
d37788a
stash 4 - pclk
ianrrees Jul 26, 2025
c32916b
stash 4 - xosc and xosc32k
ianrrees Jul 27, 2025
1a9f1ab
Remove nvmctrl from GCLK init f/u stash 4 reset
ianrrees Jul 27, 2025
ec2498c
Fix thumbv6 reset detail
ianrrees Jul 27, 2025
8a36df5
more stash 4 - gclk
ianrrees Jul 27, 2025
caf8daf
stash 5 - osc32k
ianrrees Jul 24, 2025
b720805
stash 5 - reset, stash 5 - osculp32k
ianrrees Jul 27, 2025
83fedf6
remainder of stash 4 - gclk
ianrrees Jul 27, 2025
d50486c
Add xosc to devices table
ianrrees Jul 28, 2025
3c424b4
stash 5 - dpll
ianrrees Jul 28, 2025
044ac1e
minor doc fix from stash 5 - finer-grained configuration
ianrrees Jul 28, 2025
5f15847
stash 5 - pclk
ianrrees Jul 28, 2025
3fcbb8e
stash 5 - xosc32k
ianrrees Jul 28, 2025
4355c28
stash 4 - gpio
ianrrees Jul 28, 2025
710d688
fix build for SAMD11
ianrrees Jul 28, 2025
b769f11
L variants don't have xosc32k
ianrrees Jul 28, 2025
30fc013
Fixes for SAMD21E
ianrrees Jul 28, 2025
3807c6e
Fix builds for smaller SAMD51
ianrrees Jul 28, 2025
623259f
Build on stable Rust
ianrrees Jul 29, 2025
7feb113
Update Feather M4 examples
ianrrees Jul 29, 2025
9c816cb
Deduplicate feather_m4 and metro_m4 blinky_rtc example
ianrrees Jul 29, 2025
c362dba
Deduplicate feather_m4 and metro_m4 adc example
ianrrees Jul 29, 2025
7a9b29b
Update pygamer blinky_rtic example
ianrrees Jul 29, 2025
fe2959d
Update atsame54_xpro examples
ianrrees Jul 30, 2025
e85d94d
dfll tidy
ianrrees Jul 30, 2025
311c44b
TEMPORARY enable clock v2 for thumbv6 in delay
ianrrees Jul 30, 2025
2b9ba81
Metro M0 blinky_basic update to clock v2
ianrrees Jul 30, 2025
5ca00a9
Clippy
ianrrees Jul 30, 2025
3494395
Fix polarity in DPLL wait_enabled()
ianrrees Aug 1, 2025
3e16c94
Fix missing ID field in GCLK divider selection
ianrrees Aug 1, 2025
09584a5
GCLK refactor
ianrrees Aug 1, 2025
08df818
GCLK refactor to update entire GENCTRL
ianrrees Aug 9, 2025
b777ade
bsp(atsame54_xpro): Fix example
ianrrees Aug 9, 2025
1bd2100
Documentation warnings for SAMD21G
ianrrees Aug 16, 2025
23f1461
More doc fixes
ianrrees Aug 16, 2025
0fffb1d
Formatting, minor fix in /rustfmt.sh
ianrrees Aug 16, 2025
b1c04c9
PCLK source ID can be either type-checked or runtime-checked
jbeaurivage Jan 17, 2026
2b91312
ADC takes impl Into<DynPclk>
jbeaurivage Jan 18, 2026
774784a
Fix docs
jbeaurivage Jan 25, 2026
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2 changes: 2 additions & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,8 @@ members = [
"pac/*",
"boards/*",
]
# Fragments of example files, referenced by `include!()` from BSP examples
exclude = ["boards/examples"]

[profile.dev]
debug = true
Expand Down
12 changes: 9 additions & 3 deletions atsamd-hal-macros/devices.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,9 @@ families:
- serial-numbers
- dsu
- clock
- gclk
- xosc32k
- xosc: { count: 1 }
- gclk: { count: 6 }
- pm
- sysctrl
- wdt
Expand Down Expand Up @@ -53,7 +55,9 @@ families:
- serial-numbers
- dsu
- clock
- gclk
- xosc32k: { except: ["samd21el", "samd21gl"] }
- xosc: { count: 1 }
- gclk: { count: 8 }
- pm
- sysctrl
- wdt
Expand Down Expand Up @@ -96,7 +100,9 @@ families:
- cmcc
- dsu
- clock
- gclk
- xosc32k
- xosc: { count: 2 }
- gclk: { count: 12 }
- mclk
- rstc
- ramecc
Expand Down
18 changes: 5 additions & 13 deletions boards/atsame54_xpro/examples/blinky_rtic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

use atsame54_xpro as bsp;
use bsp::hal;
use hal::clock::v2::{clock_system_at_reset, osculp32k::OscUlp1k, rtcosc::RtcOsc};
use hal::clock::v2::{clock_system_at_reset, rtcosc::RtcOsc};
use hal::prelude::*;
use hal::rtc::rtic::rtc_clock;
use panic_rtt_target as _;
Expand All @@ -27,26 +27,18 @@ mod app {

#[init]
fn init(ctx: init::Context) -> (Shared, Local) {
let mut device = ctx.device;
let device = ctx.device;
let mut core: rtic::export::Peripherals = ctx.core;

rtt_init_print!();

let (_buses, clocks, tokens) = clock_system_at_reset(
device.oscctrl,
device.osc32kctrl,
device.gclk,
device.mclk,
&mut device.nvmctrl,
);

// Enable the 1 kHz clock from the internal 32 kHz source
let (osculp1k, _) = OscUlp1k::enable(tokens.osculp32k.osculp1k, clocks.osculp32k_base);
let (_buses, clocks, tokens) =
clock_system_at_reset(device.oscctrl, device.osc32kctrl, device.gclk, device.mclk);

// Enable the RTC clock with the 1 kHz source.
// Note that currently the proof of this (the `RtcOsc` instance) is not
// required to start the monotonic.
let _ = RtcOsc::enable(tokens.rtcosc, osculp1k);
let _ = RtcOsc::enable(tokens.rtcosc, clocks.osculp.osculp1k);

// Start the monotonic
Mono::start(device.rtc);
Expand Down
12 changes: 4 additions & 8 deletions boards/atsame54_xpro/examples/mcan.rs
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@

use atsame54_xpro as bsp;
use bsp::hal;
use clock::{osculp32k::OscUlp1k, rtcosc::RtcOsc};
use clock::rtcosc::RtcOsc;
use hal::clock::v2 as clock;
use hal::eic::{Ch15, Eic, ExtInt, Sense};
use hal::gpio::{Interrupt as GpioInterrupt, *};
Expand Down Expand Up @@ -83,7 +83,7 @@ type Aux = mcan::bus::Aux<
clock::types::Can1,
hal::can::Dependencies<
clock::types::Can1,
clock::gclk::Gclk0Id,
clock::pclk::PclkSource<clock::gclk::Gclk0Id>,
bsp::Ata6561Rx,
bsp::Ata6561Tx,
bsp::pac::Can1,
Expand Down Expand Up @@ -115,7 +115,7 @@ mod app {
can_memory: SharedMemory<Capacities> = SharedMemory::new()
])]
fn init(ctx: init::Context) -> (Shared, Local) {
let mut device = ctx.device;
let device = ctx.device;

rtt_init_print!();
rprintln!("Application up!");
Expand All @@ -125,16 +125,12 @@ mod app {
device.osc32kctrl,
device.gclk,
device.mclk,
&mut device.nvmctrl,
);

// Enable the 1 kHz clock from the internal 32 kHz source
let (osculp1k, _) = OscUlp1k::enable(tokens.osculp32k.osculp1k, clocks.osculp32k_base);

// Enable the RTC clock with the 1 kHz source.
// Note that currently the proof of this (the `RtcOsc` instance) is not
// required to start the monotonic.
let _ = RtcOsc::enable(tokens.rtcosc, osculp1k);
let _ = RtcOsc::enable(tokens.rtcosc, clocks.osculp.osculp1k);

// Start the monotonic
Mono::start(device.rtc);
Expand Down
63 changes: 63 additions & 0 deletions boards/examples/m4-adc.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
// This file is included by one or more BSP examples. In normal usage, firmware
// source code needs to start with something like:
//
// ```
// #![no_std]
// #![no_main]
// use feather_m4 as bsp;
//```

use atsamd_hal::adc::AdcBuilder;

use bsp::hal;
use bsp::pac;

#[cfg(not(feature = "use_semihosting"))]
use panic_halt as _;
#[cfg(feature = "use_semihosting")]
use panic_semihosting as _;

use bsp::entry;
use bsp::Pins;
use pac::{CorePeripherals, Peripherals};

use hal::{
adc::{Accumulation, Prescaler},
clock::v2::{clock_system_at_reset, pclk::Pclk},
};

#[entry]
fn main() -> ! {
let peripherals = Peripherals::take().unwrap();
let _core = CorePeripherals::take().unwrap();

let pins = Pins::new(peripherals.port);

let (mut buses, clocks, tokens) = clock_system_at_reset(
peripherals.oscctrl,
peripherals.osc32kctrl,
peripherals.gclk,
peripherals.mclk,
);

// Enable the ADC0 ABP clock...
let apb_adc0 = buses.apb.enable(tokens.apbs.adc0);
// ...and enable the ADC0 PCLK. Both of these are required for the
// ADC to run.
let (pclk_adc0, _gclk0) = Pclk::enable(tokens.pclks.adc0, clocks.gclk0);

let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
.with_clock_cycles_per_sample(5)
// Overruns if clock divider < 32 in debug mode
.with_clock_divider(Prescaler::Div32)
.with_vref(atsamd_hal::adc::Reference::Arefa)
.enable(peripherals.adc0, apb_adc0, pclk_adc0)
.unwrap();
let mut adc_pin = pins.a0.into_alternate();

loop {
let _res = adc.read(&mut adc_pin);
#[cfg(feature = "use_semihosting")]
let _ = cortex_m_semihosting::hprintln!("ADC value: {}", _res);
}
}
82 changes: 82 additions & 0 deletions boards/examples/m4-blinky_rtic.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,82 @@
// Blink an led using an RTIC software task and the RTC-based monotonic.
//
// This file is included by one or more BSP examples. In normal usage, firmware
// source code needs to start with something like:
//
// ```
// #![no_std]
// #![no_main]
// use feather_m4 as bsp;
//```

use bsp::{hal, Pins, RedLed};
#[cfg(not(feature = "use_semihosting"))]
use panic_halt as _;
#[cfg(feature = "use_semihosting")]
use panic_semihosting as _;

use hal::clock::v2::{clock_system_at_reset, rtcosc::RtcOsc};
use hal::prelude::*;
use hal::rtc::rtic::rtc_clock;
use rtic::app;

hal::rtc_monotonic!(Mono, rtc_clock::Clock1k);

#[app(device = bsp::pac, dispatchers = [EVSYS_0])]
mod app {
use super::*;

#[local]
struct Resources {}

#[shared]
struct Shared {
// The LED could be a local resource, since it is only used in one task
// But we want to showcase shared resources and locking
red_led: RedLed,
}

#[init]
fn init(cx: init::Context) -> (Shared, Resources) {
let device = cx.device;
let mut core: rtic::export::Peripherals = cx.core;

// Use v2 of the clocks API so that we can set the RTC clock source
let (_, clocks, tokens) =
clock_system_at_reset(device.oscctrl, device.osc32kctrl, device.gclk, device.mclk);

// Enable the RTC clock with the internal 1 kHz source.
// Note that currently the proof of this (the `RtcOsc` instance) is not
// required to start the monotonic.
let _ = RtcOsc::enable(tokens.rtcosc, clocks.osculp.osculp1k);

// Start the monotonic
Mono::start(device.rtc);

let pins = Pins::new(device.port);

// We can use the RTC in standby for maximum power savings
core.SCB.set_sleepdeep();

blink_led::spawn().ok().unwrap();

(
Shared {
red_led: pins.d13.into_push_pull_output(),
},
Resources {},
)
}

/// This function is spawned and never returns.
#[task(priority = 1, shared=[red_led])]
async fn blink_led(mut cx: blink_led::Context) {
loop {
// If the LED were a local resource, the lock would not be necessary
cx.shared.red_led.lock(|led| {
led.toggle().unwrap();
});
Mono::delay(400u64.millis()).await;
}
}
}
56 changes: 1 addition & 55 deletions boards/feather_m4/examples/adc.rs
Original file line number Diff line number Diff line change
@@ -1,59 +1,5 @@
#![no_std]
#![no_main]

use atsamd_hal::adc::AdcBuilder;
use feather_m4 as bsp;

use bsp::hal;
use bsp::pac;

#[cfg(not(feature = "use_semihosting"))]
use panic_halt as _;
#[cfg(feature = "use_semihosting")]
use panic_semihosting as _;

use bsp::entry;
use bsp::Pins;
use pac::{CorePeripherals, Peripherals};

use hal::{
adc::{Accumulation, Adc, Prescaler, Resolution},
clock::v2::{clock_system_at_reset, pclk::Pclk},
};

#[entry]
fn main() -> ! {
let mut peripherals = Peripherals::take().unwrap();
let _core = CorePeripherals::take().unwrap();

let pins = Pins::new(peripherals.port);

let (mut buses, clocks, tokens) = clock_system_at_reset(
peripherals.oscctrl,
peripherals.osc32kctrl,
peripherals.gclk,
peripherals.mclk,
&mut peripherals.nvmctrl,
);

// Enable the ADC0 ABP clock...
let apb_adc0 = buses.apb.enable(tokens.apbs.adc0);
// ...and enable the ADC0 PCLK. Both of these are required for the
// ADC to run.
let (pclk_adc0, _gclk0) = Pclk::enable(tokens.pclks.adc0, clocks.gclk0);

let mut adc = AdcBuilder::new(Accumulation::single(atsamd_hal::adc::AdcResolution::_12))
.with_clock_cycles_per_sample(5)
// Overruns if clock divider < 32 in debug mode
.with_clock_divider(Prescaler::Div32)
.with_vref(atsamd_hal::adc::Reference::Arefa)
.enable(peripherals.adc0, apb_adc0, &pclk_adc0)
.unwrap();
let mut adc_pin = pins.a0.into_alternate();

loop {
let res = adc.read(&mut adc_pin);
#[cfg(feature = "use_semihosting")]
cortex_m_semihosting::hprintln!("ADC value: {}", res);
}
}
include!("../../examples/m4-adc.rs");
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