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Linker and makefile edits
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@fcayci
fcayci committed Apr 25, 2017
1 parent fff679e commit a38f744
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Showing 15 changed files with 96 additions and 130 deletions.
6 changes: 4 additions & 2 deletions adc/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g3 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
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32 changes: 9 additions & 23 deletions adc/stm32.ld
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Original file line number Diff line number Diff line change
@@ -1,44 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text)
*(.text*) /* Program code */
*(.gnu.linkonce.t.*)
. = ALIGN(4);
*(.rodata)
*(.rodata*) /* Read only data */
*(.gnu.linkonce.r.*)
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data)
*(.data*) /* Read-write initialized data */
*(.gnu.linkonce.d.*)
. = ALIGN(4);
} >ram AT > rom
} >ram AT >rom

.bss :
{
*(.bss)
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
6 changes: 4 additions & 2 deletions clock/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g3 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
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24 changes: 9 additions & 15 deletions clock/stm32.ld
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Original file line number Diff line number Diff line change
@@ -1,36 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read only data */
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
} >ram
} >ram AT >rom

.bss :
{
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
6 changes: 4 additions & 2 deletions ext_int/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g3 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
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24 changes: 9 additions & 15 deletions ext_int/stm32.ld
View file
Original file line number Diff line number Diff line change
@@ -1,36 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read only data */
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
} >ram
} >ram AT >rom

.bss :
{
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
6 changes: 4 additions & 2 deletions pwm/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g0 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
Expand Down
24 changes: 9 additions & 15 deletions pwm/stm32.ld
View file
Original file line number Diff line number Diff line change
@@ -1,36 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read only data */
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
} >ram
} >ram AT >rom

.bss :
{
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
6 changes: 4 additions & 2 deletions systick/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g3 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
Expand Down
24 changes: 9 additions & 15 deletions systick/stm32.ld
View file
Original file line number Diff line number Diff line change
@@ -1,36 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read only data */
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
} >ram
} >ram AT >rom

.bss :
{
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
8 changes: 5 additions & 3 deletions systick/systick.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -158,9 +158,11 @@ int32_t main(void)
GPIOD->ODR |= 0x0000; // 0x0002
GPIOE->ODR |= 0x4000;

// Initialize systick with 1000000
// Disable interrupt
init_systick(1000000, 0);
// Initialize systick without interrupt
init_systick(1000, 0);
// Initialize systick with interrupt
// NOTE: comment out inside while loop
//init_systick(1000000, 1);

while(1){
delay_ms(1000); // 1 second
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6 changes: 4 additions & 2 deletions timer/makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,13 @@ LINKER_SCRIPT = stm32.ld

CFLAGS += -mcpu=cortex-m3 -mthumb # Processor setup
CFLAGS += -O0 # Optimization is off
CFLAGS += -g3 # Generate debug information
#CFLAGS += -g3 # Generate debug information
CFLAGS += -fno-common -Wall
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections

LDFLAGS += -nostartfiles -T$(LINKER_SCRIPT)
LDFLAGS += -nostartfiles
LDFLAGS += --specs=nosys.specs
LDFLAGS += -T$(LINKER_SCRIPT)

CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
Expand Down
24 changes: 9 additions & 15 deletions timer/stm32.ld
View file
Original file line number Diff line number Diff line change
@@ -1,36 +1,30 @@
ENTRY(main)

MEMORY {
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
}

ENTRY(main)

SECTIONS {
. = ORIGIN(rom); /* From 0x08000000 */

.text :
{
*(.vectors) /* Vector table */
*(.text*) /* Program code */
. = ALIGN(4);
*(.rodata*) /* Read only data */
KEEP(*(.vectors)) /* Vector table */
*(.text*) /* Program code */
*(.rodata*) /* Read only data */
. = ALIGN(4);
} >rom

. = ORIGIN(ram); /* From 0x20000000 */

.data :
{
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
} >ram
} >ram AT >rom

.bss :
{
. = ALIGN(4);
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
} >ram AT > rom

. = ALIGN(4);
end = .;
} >ram
}
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