fake layout example

act/test/userdef/30.act

@@ -0,0 +1,20 @@
+defproc inv (bool? i; bool! o)
+{
+  prs {
+    i => o-
+  }
+}
+
+template<pint drive>
+defproc szinv <: inv()
+{
+  sizing {
+     o {-drive}
+  }
+}
+
+defproc INV1 <: szinv<1> () { }
+defproc INV2 <: szinv<2> () { }
+
+INV1 x1;
+INV2 x2;

tech/layout.conf

@@ -0,0 +1,219 @@
+#
+#
+# Sample technology file for SCMOS_SUBM (nwell, 3 metal layers)
+#
+#
+begin info
+  string name "SCN3N_SUBM.30 rules"
+  string date "Created on Feb 26, 2018 by Rajit Manohar"
+end
+
+begin general
+  real scale 300           # lambda=0.30um
+  int metals 3
+end
+
+begin diff
+  string_table types "svt"          # only svt devices
+  string_table ptype "pdiff"        # p diffusion
+  string_table ntype "ndiff"        # n diffusion
+  string_table pfet  "ptransistor"  # fets
+  string_table pfet_well "nwell:nndiff"  # well for p-fet, and nplus diff
+  string_table nfet  "ntransistor"  # fets
+  string_table nfet_well "pwell:ppdiff"  # pwell, pplus diff
+end
+
+begin materials
+  begin pdiff
+    int width 3
+    int_table spacing 3
+    int_table oppspacing 12
+    int polyspacing 1
+    int notchspacing 1   # same as normal spacing
+    int_table overhang 3 # fixed overhang 
+    begin via
+      int edge 1
+      int fet 2
+    end
+  end
+
+  begin ppdiff
+    int width 3
+    int_table spacing 4
+    int_table oppspacing 12
+    int polyspacing 1
+    int diffspacing 3
+  end
+
+
+  # same rules as pdiff in this process
+  begin ndiff
+    int width 3
+    int_table spacing 3
+    int_table oppspacing 12
+    int polyspacing 1
+    int notchspacing 1   # same as normal spacing
+    int_table overhang 3 # fixed overhang 
+    begin via
+      int edge 1
+      int fet 2
+    end
+  end
+
+  begin nndiff
+    int width 3
+    int_table spacing 4
+    int_table oppspacing 12
+    int polyspacing 1
+    int diffspacing 3
+  end
+
+
+  begin ptransistor
+    int width 2
+    int_table spacing 3
+  end
+
+  begin ntransistor
+    int width 2
+    int_table spacing 3
+  end
+
+  begin nwell
+    int width 10
+    int_table spacing 6
+    int_table oppspacing 0
+    int overhang 6
+    int overhang_welldiff 3
+    int plug_dist 500
+  end
+
+  begin pwell
+    int width 10
+    int_table spacing 6
+    int_table oppspacing 0
+    int overhang 6
+    int overhang_welldiff 3
+    int plug_dist 500
+  end
+
+
+  begin polysilicon
+    int width 2
+    int_table spacing 3
+    # no pitch rules
+    # no direction rules
+    # int direction 0 = any, 1 = vert only, 2 = horiz only
+    int direction 0
+    int minarea 4
+    int minjog 0
+    int endofline 0
+    int_table overhang 2
+    int_table notch_overhang 2 # same as normal overhang
+
+    begin via
+       int_table nspacing 2
+       int_table pspacing 2
+    end
+  end
+
+  begin metal
+    begin thin
+       int_table width 4
+       int_table spacing 4
+       int pitch 8
+       int minarea 9
+       int minjog 0
+       int endofline 0
+       int direction 0
+    end
+
+    begin thick
+       int_table width 6
+       int_table spacing 4
+       int pitch 10
+       int minarea 25
+       int minjog 0
+       int endofline 0
+       int direction 0
+    end
+
+    string m1 "thin"
+    string m2 "thin"
+    string m3 "thick"
+    string m4 "thin"
+    string m5 "thick"
+  end
+end
+
+begin vias
+  # now with via templates
+  begin ct_to_active
+     int width 2
+     int spacing 3
+     begin surround
+        int up 1
+        int dn 1
+     end
+  end
+
+  begin via_sm
+     int width 2
+     int spacing 3
+     begin surround
+        int up 1
+        int dn 1
+     end
+  end
+
+  begin via_mid
+     int width 2
+     int spacing 3
+     begin surround
+        int up 1
+        int dn 1
+     end
+  end
+
+  string polysilicon "ct_to_active"
+  string polysilicon_name "gc"
+  string ndiff "ct_to_active"
+  string ndiff_name "gc"
+  string pdiff "ct_to_active"
+  string pdiff_name "gc"
+  string nwell "ct_to_active"
+  string nwell_name "gc"
+  string pwell "ct_to_active"
+  string pwell_name "gc"
+  string nndiff "ct_to_active"
+  string nndiff_name "gc"
+  string ppdiff "ct_to_active"
+  string ppdiff_name "gc"
+
+  string m1 "via_sm"
+  string m1_name "v1"
+  string m2 "via_sm"
+  string m2_name "v2"
+
+end
+
+
+begin lefdef
+  string version "5.6"
+  int micron_conversion 2000
+  real manufacturing_grid 0.0005
+  begin metal_align
+     int x_dim 2
+     int y_dim 1
+  end
+
+  # if 0, then metal2, 4, 6, ... are horizontal (even metal layers)
+  # if 1, then metal1, 3, 5, ... are horizontal (odd metal layers)
+  int horiz_metal 0
+  # pins on metal2
+  int pin_layer 2
+
+  # import .rect files, if found
+  int rect_import 0
+
+end