cores: verify all cores work on icebreaker

gateware/cores/bitcrush.sv

@@ -27,6 +27,7 @@ module bitcrush #(
 );
 
 logic signed [W-1:0] mask;
+logic signed [W-1:0] out0;
 logic signed [W-1:0] out1;
 logic signed [W-1:0] out2;
 logic signed [W-1:0] out3;
@@ -45,13 +46,14 @@ assign mask = (sample_in0 > 4*5000) ? 16'b1111111111111111 :
 
 always_ff @(posedge clk) begin
     if (strobe) begin
+        out0 <= sample_in0;
         out1 <= sample_in1 & mask;
         out2 <= sample_in2 & mask;
         out3 <= sample_in3 & mask;
     end
 end
 
-assign sample_out0 = sample_in0;
+assign sample_out0 = out0;
 assign sample_out1 = out1;
 assign sample_out2 = out2;
 assign sample_out3 = out3;

gateware/cores/pitch_shift.sv

@@ -14,7 +14,7 @@ module pitch_shift #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,
@@ -29,7 +29,8 @@ module pitch_shift #(
 transpose #(
     .W(W)
 ) transpose_instance (
-    .sample_clk(sample_clk),
+    .clk,
+    .strobe,
     .pitch(sample_in1),
     .sample_in(sample_in0),
     .sample_out(sample_out1)

gateware/cores/sampler.sv

@@ -18,7 +18,7 @@ module sampler #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,
@@ -46,21 +46,23 @@ logic [$clog2(N_SAMPLES):0] sample_pos = 0;
 // Value of the last sample at sample_pos, synchronized to sample_clk.
 logic [W-1:0] cur_sample = 16'h0;
 
-always_ff @(posedge sample_clk) begin
-    sclkdiv <= sclkdiv + 1;
-    if (sclkdiv % 2 == 0 && sample_pos <= N_SAMPLES) begin
-        sample_pos <= sample_pos + 1;
-    end
-    if (sample_in0 < TRIGGER_HI) begin
-        // Hold first sample as long as we have no trigger. As
-        // soon as it goes high, we 'allow' playback.
-        sample_pos <= 0;
-    end
-    if (sample_pos < N_SAMPLES) begin
-        cur_sample <= wav_samples[sample_pos[$clog2(N_SAMPLES)-1:0]];
-    end else begin
-        // If we go past the end of the sample, hold 0V at the output.
-        cur_sample <= 16'h0;
+always_ff @(posedge clk) begin
+    if (strobe) begin
+        sclkdiv <= sclkdiv + 1;
+        if (sclkdiv % 2 == 0 && sample_pos <= N_SAMPLES) begin
+            sample_pos <= sample_pos + 1;
+        end
+        if (sample_in0 < TRIGGER_HI) begin
+            // Hold first sample as long as we have no trigger. As
+            // soon as it goes high, we 'allow' playback.
+            sample_pos <= 0;
+        end
+        if (sample_pos < N_SAMPLES) begin
+            cur_sample <= wav_samples[sample_pos[$clog2(N_SAMPLES)-1:0]];
+        end else begin
+            // If we go past the end of the sample, hold 0V at the output.
+            cur_sample <= 16'h0;
+        end
     end
 end
 

gateware/cores/seqswitch.sv

@@ -18,7 +18,7 @@ module seqswitch #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,
@@ -43,43 +43,44 @@ logic last_state_hi = 1'b0;
 // Current routing state of the sequential switch.
 logic [1:0] switch_state = 2'b00;
 
-always_ff @(posedge sample_clk) begin
+always_ff @(posedge clk) begin
+    if (strobe) begin
+        // Rising edge of clock.
+        if (sample_in0 > SCHMITT_HI && !last_state_hi) begin
+            last_state_hi <= 1'b1;
 
-    // Rising edge of clock.
-    if (sample_in0 > SCHMITT_HI && !last_state_hi) begin
-        last_state_hi <= 1'b1;
+            // Update switch routing on a rising edge.
+            if (switch_state == 2'b10) switch_state <= 2'b00;
+            else switch_state <= switch_state + 1;
+        end
 
-        // Update switch routing on a rising edge.
-        if (switch_state == 2'b10) switch_state <= 2'b00;
-        else switch_state <= switch_state + 1;
-    end
+        // Falling edge of clock.
+        if (sample_in0 < SCHMITT_LO && last_state_hi) begin
+            last_state_hi <= 1'b0;
+        end
 
-    // Falling edge of clock.
-    if (sample_in0 < SCHMITT_LO && last_state_hi) begin
-        last_state_hi <= 1'b0;
+        // Samples mirrored at audio rate based on current routing.
+        case (switch_state)
+            2'b00: begin
+                sample_out1 <= sample_in1;
+                sample_out2 <= sample_in2;
+                sample_out3 <= sample_in3;
+            end
+            2'b01: begin
+                sample_out1 <= sample_in2;
+                sample_out2 <= sample_in3;
+                sample_out3 <= sample_in1;
+            end
+            2'b10: begin
+                sample_out1 <= sample_in3;
+                sample_out2 <= sample_in1;
+                sample_out3 <= sample_in2;
+            end
+            default: begin
+                // State is never entered
+            end
+        endcase
     end
-
-    // Samples mirrored at audio rate based on current routing.
-    case (switch_state)
-        2'b00: begin
-            sample_out1 <= sample_in1;
-            sample_out2 <= sample_in2;
-            sample_out3 <= sample_in3;
-        end
-        2'b01: begin
-            sample_out1 <= sample_in2;
-            sample_out2 <= sample_in3;
-            sample_out3 <= sample_in1;
-        end
-        2'b10: begin
-            sample_out1 <= sample_in3;
-            sample_out2 <= sample_in1;
-            sample_out3 <= sample_in2;
-        end
-        default: begin
-            // State is never entered
-        end
-    endcase
 end
 
 assign sample_out0 = sample_in0;

gateware/cores/touch_cv.sv

@@ -15,7 +15,7 @@ module touch_cv #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,

gateware/cores/util/transpose.sv

@@ -13,7 +13,8 @@ module transpose #(
     parameter WINDOW = 512,
     parameter XFADE = 128
 )(
-    input sample_clk,
+    input clk,
+    input strobe,
     input signed [W-1:0] pitch,
     input signed [W-1:0] sample_in,
     output logic signed [W-1:0] sample_out
@@ -43,42 +44,46 @@ logic signed [XFADE_BITS:0] env1_reg;
 // have no interpolation between integer delay line steps.
 
 delayline #(W, DELAYLINE_LEN) delay_0 (
-    .sample_clk(sample_clk),
+    .clk,
+    .strobe,
     .delay({1'b0, delay_int}),
     .in(sample_in),
     .out(delay_out0)
 );
 
 delayline #(W, DELAYLINE_LEN) delay_1(
-    .sample_clk(sample_clk),
+    .clk,
+    .strobe,
     .delay({1'b0, delay_int}+WINDOW),
     .in(sample_in),
     .out(delay_out1)
 );
 
-always_ff @(posedge sample_clk) begin
-    // The value we increment `d` by here is actually the 'pitch shift' amount.
-    // walking up the delay lines some amount faster or slower than usual.
-    //
-    // TODO: Make this track 1V/oct.
-    delay_frac <= delay_frac + (pitch >>> 8);
+always_ff @(posedge clk) begin
+    if (strobe) begin
+        // The value we increment `d` by here is actually the 'pitch shift' amount.
+        // walking up the delay lines some amount faster or slower than usual.
+        //
+        // TODO: Make this track 1V/oct.
+        delay_frac <= delay_frac + (pitch >>> 8);
 
-    if (delay_int < XFADE) begin
-        env0 <= delay_int[XFADE_BITS:0];
-        env1 <= (XFADE-1) - delay_int[XFADE_BITS:0];
-    end else begin
-        env0 <= XFADE-1;
-        env1 <= 0;
-    end
+        if (delay_int < XFADE) begin
+            env0 <= delay_int[XFADE_BITS:0];
+            env1 <= (XFADE-1) - delay_int[XFADE_BITS:0];
+        end else begin
+            env0 <= XFADE-1;
+            env1 <= 0;
+        end
 
-    // Envelopes need to be delayed by 1 sample to avoid discontinuity as we
-    // swap between the 2 delay line feeds.
-    env0_reg <= env0;
-    env1_reg <= env1;
+        // Envelopes need to be delayed by 1 sample to avoid discontinuity as we
+        // swap between the 2 delay line feeds.
+        env0_reg <= env0;
+        env1_reg <= env1;
 
-    // TODO: pipeline these multiplies.
-    sample_out <= W'(((W+XFADE_BITS)'(delay_out0) * (W+XFADE_BITS)'(env0_reg)) >>> XFADE_BITS) +
-                  W'(((W+XFADE_BITS)'(delay_out1) * (W+XFADE_BITS)'(env1_reg)) >>> XFADE_BITS);
+        // TODO: pipeline these multiplies.
+        sample_out <= W'(((W+XFADE_BITS)'(delay_out0) * (W+XFADE_BITS)'(env0_reg)) >>> XFADE_BITS) +
+                      W'(((W+XFADE_BITS)'(delay_out1) * (W+XFADE_BITS)'(env1_reg)) >>> XFADE_BITS);
+    end
 end
 
 endmodule

gateware/cores/util/wavetable_osc.sv

@@ -5,7 +5,8 @@ module wavetable_osc #(
     parameter WAVETABLE_SIZE = 256
 )(
     input rst,
-    input sample_clk,
+    input clk,
+    input strobe,
     input [31:0] wavetable_inc,
     output logic signed [W-1:0] out
 );
@@ -16,13 +17,15 @@ initial $readmemh(WAVETABLE_PATH, wavetable);
 // Position in wavetable - N.F fixed-point where BIT_START is size of F.
 logic [31:0] wavetable_pos = 0;
 
-always_ff @(posedge sample_clk) begin
-    if (rst) begin
-        wavetable_pos <= 0;
-    end else begin
-        wavetable_pos <= wavetable_pos + wavetable_inc;
-        // Take top N bits of wavetable_pos as output.
-        out <= wavetable[wavetable_pos[FRAC_BITS+$clog2(WAVETABLE_SIZE)-1:FRAC_BITS]];
+always_ff @(posedge clk) begin
+    if (strobe) begin
+        if (rst) begin
+            wavetable_pos <= 0;
+        end else begin
+            wavetable_pos <= wavetable_pos + wavetable_inc;
+            // Take top N bits of wavetable_pos as output.
+            out <= wavetable[wavetable_pos[FRAC_BITS+$clog2(WAVETABLE_SIZE)-1:FRAC_BITS]];
+        end
     end
 end
 

gateware/cores/vca.sv

@@ -19,7 +19,7 @@ module vca #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,

gateware/cores/vco.sv

@@ -15,7 +15,7 @@ module vco #(
 )(
     input rst,
     input clk,
-    input sample_clk,
+    input strobe,
     input signed [W-1:0] sample_in0,
     input signed [W-1:0] sample_in1,
     input signed [W-1:0] sample_in2,
@@ -39,13 +39,15 @@ initial $readmemh(V_OCT_LUT_PATH, v_oct_lut);
 logic signed [W-1:0] lut_index = 0;
 logic signed [W-1:0] lut_index_clamp_lo = 0;
 
-always_ff @(posedge sample_clk) begin
-    if (rst) begin
-        lut_index <= 0;
-        lut_index_clamp_lo <= 0;
-    end else begin
-        lut_index <= sample_in0 >>> 6;
-        lut_index_clamp_lo <= lut_index < 0 ? 0 : lut_index;
+always_ff @(posedge clk) begin
+    if (strobe) begin
+        if (rst) begin
+            lut_index <= 0;
+            lut_index_clamp_lo <= 0;
+        end else begin
+            lut_index <= sample_in0 >>> 6;
+            lut_index_clamp_lo <= lut_index < 0 ? 0 : lut_index;
+        end
     end
 end
 
@@ -55,8 +57,9 @@ wavetable_osc #(
     .WAVETABLE_PATH(WAVETABLE_PATH),
     .WAVETABLE_SIZE(WAVETABLE_SIZE)
 ) osc_0 (
-    .rst(rst),
-    .sample_clk(sample_clk),
+    .rst,
+    .clk,
+    .strobe,
     .wavetable_inc(32'(v_oct_lut[$clog2(V_OCT_LUT_SIZE)'(lut_index_clamp_lo)])),
     .out(sample_out0)
 );

gateware/top.sv

@@ -34,7 +34,7 @@ logic [7:0] strobe_clkdiv;
 
 always_ff @(posedge clk_256fs) begin
     if (rst) begin
-        strobe_clkdiv = 8'h0;
+        strobe_clkdiv <= 8'h0;
     end else begin
         strobe_clkdiv <= strobe_clkdiv + 1;
     end