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[VERILOG] Basic Verilog Testflow #70

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merged 4 commits into from
Mar 14, 2017
Merged

[VERILOG] Basic Verilog Testflow #70

merged 4 commits into from
Mar 14, 2017

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tqchen
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@tqchen tqchen commented Mar 14, 2017 •
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@tqchen tqchen requested a review from tmoreau89 March 14, 2017 03:04
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tmoreau89 commented Mar 14, 2017 •
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Looks good to me.

In https://github.com/tqchen/tvm/blob/tqchen/tests/verilog/test_counter.v#L7 the #() can be deleted since the module does not take in parameters.

@tmoreau89 tmoreau89 closed this Mar 14, 2017
@tqchen tqchen reopened this Mar 14, 2017
tmoreau89
tmoreau89 reviewed Mar 14, 2017
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python/tvm/addon/verilog.py Outdated


def compile_file(file_name, file_target, options=None):
"""Compile cuda code with NVCC from env.
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should be about running the verilog simulation

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fixed in next commit

tmoreau89
tmoreau89 approved these changes Mar 14, 2017
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looks good to me

@tqchen tqchen merged commit 9e660db into master Mar 14, 2017
cyx-6 added a commit to cyx-6/tvm that referenced this pull request Jul 27, 2022
@cyx-6
rest ops, Assert and globals (apache#70)
72f833b 
* rest `op`s, `Assert` and `globals`

* apply code review suggestions

* apply code review suggestions
sunggg pushed a commit to sunggg/tvm that referenced this pull request Apr 15, 2024
@csullivan
[Fix] Fix GPU build on systems without GPUs installed (apache#70)
838c4ed
csullivan added a commit to csullivan/tvm that referenced this pull request Apr 27, 2024
@csullivan
[Fixup] Reapply apache#70 after merge with upstream in apache#72 (apa…
9bb2c19 
…che#81)
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@tmoreau89 tmoreau89 tmoreau89 approved these changes

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