[Relay][Strategy] Fix arm_cpu
int8 conv2d schedule selection for 32-bit targets
#15468
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#12455 slightly altered the behaviour when selecting an int8 conv2d schedule. Previously conditions that decide which schedule to select used
is_aarch64
which checks for the existance ofaarch64
in the target triple. However, the conditions now usehas_asimd
which is true ifaarch64
exists in the target triple OR+neon
is used in the mattr.Both
conv2d_NHWC_quantized_interleaved.arm_cpu
anddepthwise_conv2d_nhwc.arm_cpu
makes calls to LLVM intrinsics that require bothaarch64
and+neon
. But in the case of the targetrasp4b
, the updated conditions result in compilation failure since the target has+neon
but doesn't haveaarch64
in the target triple. The conditions have been updated to fix the compilation failure.Likewise, the previous behaviour of the condition for
conv2d_nhwc_spatial_pack.arm_cpu
has been restored ensure a program with a 32-bit target can still be compiled.Finally, we should only select the
depthwise_conv2d_nhwc_dsp.arm_cpu
schedule when a backend that understandspragma_import_c
has been selected, i.e. "c".For a more detailed discussion of the issue please see: https://discuss.tvm.apache.org/t/tflite-llvm-llvm-error-when-compiling-tflite-model/15411
cc @Mousius @ashutosh-arm @ekalda @neildhickey