feature k210

arch/risc-v/Kconfig

@@ -16,6 +16,12 @@ config ARCH_CHIP_FE310
 	---help---
 		SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
 
+config ARCH_CHIP_K210
+	bool "Kendryte K210"
+	select ARCH_RV64GC
+	---help---
+		Kendryte K210 processor (RISC-V 64bit core with GC extensions)
+
 config ARCH_CHIP_NR5
 	bool "NEXT NanoRisc5"
 	select ARCH_RV32IM
@@ -39,13 +45,19 @@ config ARCH_RV32IM
 	bool
 	default n
 
+config ARCH_RV64GC
+	bool
+	default n
+
 config ARCH_FAMILY
 	string
-	default "rv32im"	if ARCH_RM32IM
+	default "rv32im"	if ARCH_RV32IM
+	default "rv64gc"	if ARCH_RV64GC
 
 config ARCH_CHIP
 	string
 	default "fe310"		if ARCH_CHIP_FE310
+	default "k210"		if ARCH_CHIP_K210
 	default "nr5m100"	if ARCH_CHIP_NR5
 	default "gap8"		if ARCH_CHIP_GAP8
 
@@ -62,9 +74,15 @@ config NR5_MPU
 if ARCH_RV32IM
 source arch/risc-v/src/rv32im/Kconfig
 endif
+if ARCH_RV64GC
+source arch/risc-v/src/rv64gc/Kconfig
+endif
 if ARCH_CHIP_FE310
 source arch/risc-v/src/fe310/Kconfig
 endif
+if ARCH_CHIP_K210
+source arch/risc-v/src/k210/Kconfig
+endif
 if ARCH_CHIP_NR5
 source arch/risc-v/src/nr5m100/Kconfig
 endif

arch/risc-v/include/irq.h

@@ -53,6 +53,10 @@
 #  include <arch/rv32im/irq.h>
 #endif
 
+#if defined(CONFIG_ARCH_RV64GC)
+#  include <arch/rv64gc/irq.h>
+#endif
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/

arch/risc-v/include/k210/chip.h

@@ -0,0 +1,36 @@
+/****************************************************************************
+ * arch/risc-v/include/k210/chip.h
+ *
+ *   Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
+ *   Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_K210_CHIP_H
+#define __ARCH_RISCV_INCLUDE_K210_CHIP_H
+
+#endif /* __ARCH_RISCV_INCLUDE_K210_CHIP_H */

arch/risc-v/include/k210/irq.h

@@ -0,0 +1,121 @@
+/****************************************************************************
+ * arch/risc-v/include/k210/irq.h
+ *
+ *   Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
+ *   Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_K210_IRQ_H
+#define __ARCH_RISCV_INCLUDE_K210_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Machine Interrupt Enable bit in mstatus register */
+
+#define MSTATUS_MIE  (0x1 << 3)
+
+/* In mie (machine interrupt enable) register */
+
+#define MIE_MTIE      (0x1 << 7)  /* Machine Timer Interrupt Enable */
+#define MIE_MEIE      (0x1 << 11) /* Machine External Interrupt Enable */
+
+/* Map RISC-V exception code to NuttX IRQ */
+
+/* IRQ 0-15 : (exception:interrupt=0) */
+
+#define K210_IRQ_IAMISALIGNED  (0) /* Instruction Address Misaligned */
+#define K210_IRQ_IAFAULT       (1) /* Instruction Address Fault */
+#define K210_IRQ_IINSTRUCTION  (2) /* Illegal Instruction */
+#define K210_IRQ_BPOINT        (3) /* Break Point */
+#define K210_IRQ_LAMISALIGNED  (4) /* Load Address Misaligned */
+#define K210_IRQ_LAFAULT       (5) /* Load Access Fault */
+#define K210_IRQ_SAMISALIGNED  (6) /* Store/AMO Address Misaligned */
+#define K210_IRQ_SAFAULT       (7) /* Store/AMO Access Fault */
+#define K210_IRQ_ECALLU        (8) /* Environment Call from U-mode */
+                                    /* 9-10: Reserved */
+
+#define K210_IRQ_ECALLM       (11) /* Environment Call from M-mode */
+                                    /* 12-15: Reserved */
+
+/* IRQ 16- : (async event:interrupt=1) */
+
+#define K210_IRQ_ASYNC        (16)
+#define K210_IRQ_MSOFT    (K210_IRQ_ASYNC + 3)  /* Machine Software Int */
+#define K210_IRQ_MTIMER   (K210_IRQ_ASYNC + 7)  /* Machine Timer Int */
+#define K210_IRQ_MEXT     (K210_IRQ_ASYNC + 11) /* Machine External Int */
+
+/* Machine Grobal External Interrupt */
+
+#define K210_IRQ_UART0    (K210_IRQ_MEXT + 33)
+
+/* Total number of IRQs */
+
+#define NR_IRQS            (K210_IRQ_UART0 + 1)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+EXTERN irqstate_t  up_irq_save(void);
+EXTERN void up_irq_restore(irqstate_t);
+EXTERN irqstate_t up_irq_enable(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_INCLUDE_K210_IRQ_H */
+

arch/risc-v/include/limits.h

@@ -87,4 +87,20 @@
 
 #endif /* defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) */
 
+#if defined(CONFIG_ARCH_RV64GC)
+
+#define LONG_MIN    (-LONG_MAX - 1)
+#define LONG_MAX    9223372036854775807L
+#define ULONG_MAX   18446744073709551615UL
+
+#define LLONG_MIN   (-LLONG_MAX - 1)
+#define LLONG_MAX   9223372036854775807LL
+#define ULLONG_MAX  18446744073709551615ULL
+
+#define PTR_MIN     (-PTR_MAX - 1)
+#define PTR_MAX     9223372036854775807
+#define UPTR_MAX    18446744073709551615U
+
+#endif
+
 #endif /* __ARCH_RISCV_INCLUDE_LIMITS_H */