aolwyn / CPU-Construction-Zone Public

The development of a RISC-style processor / computer in Verilog

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 120 Commits
CONFF.v		CONFF.v
LICENSE		LICENSE
PCincrement.v		PCincrement.v
RAM.qip		RAM.qip
RAM.v		RAM.v
RAM_info.mif		RAM_info.mif
README.md		README.md
Reg32.v		Reg32.v
ToDo.txt		ToDo.txt
add.v		add.v
add_tb.v		add_tb.v
addi_tb.v		addi_tb.v
alu.v		alu.v
alu_tb.v		alu_tb.v
and_tb.v		and_tb.v
andi_tb.v		andi_tb.v
branch_tb.v		branch_tb.v
clkDivider.v		clkDivider.v
control_unit.v		control_unit.v
cpu_tb.v		cpu_tb.v
datapath.v		datapath.v
datapath_tb.v		datapath_tb.v
divide_32.v		divide_32.v
encoder_32_5.v		encoder_32_5.v
in_out_tb.v		in_out_tb.v
jal_tb.v		jal_tb.v
jr_tb.v		jr_tb.v
ld_tb.v		ld_tb.v
ldi_tb.v		ldi_tb.v
load_tb.v		load_tb.v
logicalAnd.v		logicalAnd.v
logicalNot.v		logicalNot.v
logicalOr.v		logicalOr.v
logicalOr_tb.v		logicalOr_tb.v
marUnit.v		marUnit.v
memoryRam.v		memoryRam.v
mfhi_tb.v		mfhi_tb.v
mflo_out.v		mflo_out.v
multiply.v		multiply.v
mux_2_1.v		mux_2_1.v
mux_32_1.v		mux_32_1.v
negate.v		negate.v
ori_tb.v		ori_tb.v
rotate_R.v		rotate_R.v
select_and_encode.v		select_and_encode.v
shift_L.v		shift_L.v
shift_R.v		shift_R.v
st_tb..v		st_tb..v
subtract.v		subtract.v