dts/riscv: remove the timebase-frequency property

The `timebase-frequency` is not defined by any of the YAML binding files. There was a discussion in zephyrproject-rtos#37420 to add this property, but in the end it was rejected. This resulted in the zephyrproject-rtos#37685 feature request being created. As of now, this property is not documented anywhere so this commit removes it from the RISC-V devicetrees, as RISC-V is the only architecture that is currently defining it - and even in RISC-V not all platforms do that. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
antmicro · Jan 19, 2024 · 69d1b11 · 69d1b11
1 parent 8429398
commit 69d1b11
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diff --git a/dts/riscv/andes/andes_v5_ae350.dtsi b/dts/riscv/andes/andes_v5_ae350.dtsi
@@ -15,7 +15,6 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		timebase-frequency = <60000000>;
 		CPU0: cpu@0 {
 			compatible = "riscv";
 			device_type = "cpu";

diff --git a/dts/riscv/efinix/sapphire_soc.dtsi b/dts/riscv/efinix/sapphire_soc.dtsi
@@ -32,7 +32,6 @@
 			reg = <0>;
 			riscv,isa = "rv32ima_zicsr_zifencei";
 			status = "okay";
-			timebase-frequency = <100000000>;
 
 			hlic: interrupt-controller {
 				compatible = "riscv,cpu-intc";

diff --git a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi
@@ -12,7 +12,6 @@
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		timebase-frequency = <10000000>;
 
 		cpu@0 {
 			device_type = "cpu";

diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi
@@ -25,7 +25,6 @@
 			reg = <0>;
 			riscv,isa = "rv32ima_zicsr_zifencei";
 			status = "okay";
-			timebase-frequency = <32768>;
 		};
 	};
 	soc {

diff --git a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
@@ -16,7 +16,6 @@
 	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		timebase-frequency = <6250000>;
 		compatible = "starfive,fu74-g000";
 		cpu@0 {
 			clock-frequency = <0>;

diff --git a/dts/riscv/virt.dtsi b/dts/riscv/virt.dtsi
@@ -36,7 +36,6 @@
 	cpus {
 		#address-cells = < 0x01 >;
 		#size-cells = < 0x00 >;
-		timebase-frequency = < 10000000 >;
 
 		cpu@0 {
 			device_type = "cpu";