Skip to content
View anlit75's full-sized avatar

Highlights

  • Pro

Block or report anlit75

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

💫 Toolkit to help you get started with Spec-Driven Development

Python 18,664 1,443 Updated Sep 16, 2025

"DeepCode: Open Agentic Coding (Paper2Code & Text2Web & Text2Backend)"

Python 6,345 865 Updated Sep 14, 2025

Create beautiful mosaics from images and photos

TypeScript 179 20 Updated Dec 30, 2022

Some awesome prompts for Jules Agent

2,209 359 Updated May 21, 2025

Fair-code workflow automation platform with native AI capabilities. Combine visual building with custom code, self-host or cloud, 400+ integrations.

TypeScript 138,087 43,625 Updated Sep 16, 2025

An open-source AI agent that brings the power of Grok directly into your terminal.

TypeScript 1,672 202 Updated Sep 13, 2025

An open-source AI agent that brings the power of Gemini directly into your terminal.

TypeScript 75,309 7,987 Updated Sep 16, 2025

Example code for Verification Gentleman blog

SystemVerilog 9 4 Updated Mar 2, 2016

Integrate the DeepSeek API into popular softwares

33,812 3,769 Updated Sep 4, 2025

🎨 ASCII art library for Python

Python 2,354 152 Updated Aug 12, 2025

Master the command line, in one page

158,148 14,749 Updated Jun 25, 2024

Tests para correr openlane en actions

Verilog 5 21 Updated Dec 6, 2024
Python 23 8 Updated Sep 3, 2025

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called pr…

C++ 230 38 Updated Aug 20, 2024

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

Verilog 393 54 Updated Jul 18, 2025

2 Week Advanced Physical Design using OpenLANE/Sky130 workshop with complete RTL2GDSII flow organised by VSD as part of Level-3 of Chip Design for High School Program in collaboration with Intel India

Verilog 6 Updated Mar 27, 2024

Physical Design Flow from RTL to GDS using Opensource tools.

106 18 Updated Nov 23, 2020

Just fork & good to go! A beautiful showcase for all your GitHub repos.

HTML 1 Updated Sep 16, 2025

Just fork & good to go! A beautiful showcase for all your GitHub repos.

Python 1 Updated Mar 9, 2025

I have one 🌟; you can hover over the image to see the status.

1 Updated Feb 17, 2025

If you build software, keep a changelog.

Haml 6,372 3,589 Updated Sep 1, 2025

Web-based tool converts GitHub repository contents into a single formatted text file

JavaScript 1,522 189 Updated Aug 6, 2025

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python 1,580 401 Updated Sep 15, 2025

Tiny Tapeout 10

Verilog 10 13 Updated Mar 12, 2025

Submission template for Tiny Tapeout 10 - Verilog HDL Projects

Verilog 24 248 Updated Jun 27, 2025

The UVM written in Python

Python 450 86 Updated Jul 11, 2025

UVM实战随书源码

SystemVerilog 54 22 Updated Jan 22, 2019

⚡ Dynamically generated stats for your github readmes

JavaScript 75,908 25,967 Updated Sep 15, 2025

Dynamic Profile with github statistics, coding info (time and languages) with WakaTime and music status with the spotify API, leave a ⭐ if you like it

Markdown 502 237 Updated Sep 15, 2025

Simple AMBA VIP, Include axi/ahb/apb

SystemVerilog 27 Updated Jul 4, 2024
Next