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1. NYU-MLDA/OpenABC NYU-MLDA/OpenABC Public

   OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

   Verilog 115 20

2. NYU-MLDA/ABC-RL NYU-MLDA/ABC-RL Public

   This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

   Verilog 3 1

3. NYU-MLDA/robust-pnr-time NYU-MLDA/robust-pnr-time Public

   Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"

   Verilog 5 2

4. NYU-MLDA/ALMOST NYU-MLDA/ALMOST Public

   ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

   Verilog 2

5. NYU-MLDA/RTL_dataset NYU-MLDA/RTL_dataset Public

   Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys

   Verilog 1

6. sv-comp sv-comp Public

   Forked from sosy-lab/sv-comp

   Information to reproduce results from SV-COMP