Improve stubbing-out of the f2 and e2 stages

Lets some additional sort-of-kind-of-work until
we have the caches implemented :)

rtl/letc/core/letc_core_stage_e2.sv

@@ -36,6 +36,78 @@ module letc_core_stage_e2
     output e2_to_w_s o_e2_to_w
 );
 
-assign o_e2_to_w.valid = 1'b0;//TODO
+/* ------------------------------------------------------------------------------------------------
+ * Memory Access Logic
+ * --------------------------------------------------------------------------------------------- */
+
+logic memory_ready;
+assign memory_ready = 1'b1;//TODO
+
+//TODO implement data cache access stuffs here!
+word_t memory_rdata;
+assign memory_rdata = 32'hDEADBEEF;//TODO
+
+/* ------------------------------------------------------------------------------------------------
+ * Stage Readiness Logic
+ * --------------------------------------------------------------------------------------------- */
+
+logic stage_ready;
+always_comb begin
+    //TODO how do the flush/stall signals play into this?
+    if (i_e1_to_e2.valid && (i_e1_to_e2.memory_op != MEM_OP_NOP) && !memory_ready) begin
+        stage_ready = 1'b0;
+    end else begin
+        stage_ready = 1'b1;
+    end
+
+    o_stage_ready = stage_ready;
+end
+
+/* ------------------------------------------------------------------------------------------------
+ * Output Flop Stage
+ * --------------------------------------------------------------------------------------------- */
+
+always_ff @(posedge i_clk) begin
+    if (!i_rst_n) begin
+        o_e2_to_w.valid <= 1'b0;
+    end else begin
+        if (!i_stage_stall) begin
+            if (i_stage_flush || !stage_ready) begin//Invalidate the output/output isn't ready yet
+                o_e2_to_w.valid <= 1'b0;
+            end else begin//Chugging along, pun intended :)
+                o_e2_to_w.valid <= i_e1_to_e2.valid;
+            end
+        end
+    end
+end
+
+always_ff @(posedge i_clk) begin
+    //Save resources by not resetting the datapath; which is fine since `valid` above is reset
+    //if (i_f2_to_d.valid & !i_stage_stall) begin//More power efficient but worse for timing and area
+    if (!i_stage_stall) begin
+        o_e2_to_w.rd_src    <= i_e1_to_e2.rd_src;
+        o_e2_to_w.rd_idx    <= i_e1_to_e2.rd_idx;
+        o_e2_to_w.rd_we     <= i_e1_to_e2.rd_we;
+
+        o_e2_to_w.csr_op    <= i_e1_to_e2.csr_op;
+        o_e2_to_w.csr_idx   <= i_e1_to_e2.csr_idx;
+
+        o_e2_to_w.old_csr_value <= i_e1_to_e2.old_csr_value;
+        o_e2_to_w.alu_result    <= i_e1_to_e2.alu_result;
+        o_e2_to_w.memory_rdata  <= memory_rdata;
+    end
+end
+
+/* ------------------------------------------------------------------------------------------------
+ * Assertions
+ * --------------------------------------------------------------------------------------------- */
+
+`ifdef SIMULATION
+
+assert property (@(posedge i_clk) disable iff (!i_rst_n) !(i_stage_flush && i_stage_stall));
+
+//TODO
+
+`endif //SIMULATION
 
 endmodule : letc_core_stage_e2

rtl/letc/core/letc_core_stage_f2.sv

@@ -52,7 +52,7 @@ end
 
 always_ff @(posedge i_clk) begin
     o_f2_to_d.pc_word <= i_f1_to_f2.pc_word;
-    o_f2_to_d.instr <= instr_mem[i_f1_to_f2.fetch_addr[9:0]][31:2];
+    o_f2_to_d.instr <= instr_mem[i_f1_to_f2.fetch_addr[11:2]][31:2];
 end
 
 initial begin//TESTING this is not synthesizable (except on FPGA kinda sorta)