added parallel load to shift register

lint/filelist.f

@@ -17,6 +17,8 @@
 rtl/common/axi/axi_pkg.sv
 rtl/common/axi/axi_if.sv
 rtl/common/axi/axi_buffer.sv
+rtl/common/counter/counter.sv
+rtl/common/shift_register/shift_register.sv
 
 rtl/letc/letc_pkg.sv
 rtl/letc/letc_top.sv
@@ -54,6 +56,8 @@
 verif/nonuvm/smoke_tb.sv
 
 verif/nonuvm/common/fifo/fifo_0r1w/fifo_0r1w_tb.sv
+verif/nonuvm/common/counter/counter_tb.sv
+verif/nonuvm/common/shift_register/shift_register_tb.sv
 
 verif/nonuvm/example/example_tb.sv
 

rtl/common/counter/counter.sv

@@ -1,6 +1,6 @@
 /*
- * File:    address_counter.sv
- * Brief:   Simple module that stores a memory address value and increments it.
+ * File:    counter.sv
+ * Brief:   Simple module that stores a value and increments it.
  *
  * Copyright:
  *  Copyright (C) 2024 Eric Jessee
@@ -39,4 +39,4 @@ always_ff @(posedge i_clk) begin
     end
 end
 
-endmodule
+endmodule

rtl/common/shift_register/shift_register.sv

@@ -9,25 +9,28 @@
 */
 
 module shift_register #(
-    parameter int WIDTH = 8,
-    parameter logic [WIDTH-1:0] INIT = '0
+    parameter int WIDTH = 8
 ) (
     input logic i_clk,
     input logic i_rst_n,
 
     input logic i_sdata,
     input logic i_shift,
+    input logic i_load,
+    input logic [WIDTH-1:0] i_ldata,
 
     output logic [WIDTH-1:0] o_data,
     output logic o_carryout
-
 );
 
 logic [WIDTH-1:0] data;
 
 always_ff @(posedge i_clk) begin
     if (!i_rst_n) begin
-        data <= INIT;
+        data <= '0;
+        o_carryout <= 1'b0;
+    end else if (i_load) begin
+        data <= i_ldata;
         o_carryout <= 1'b0;
     end else if (i_shift) begin
         data[0] <= i_sdata;
@@ -42,4 +45,4 @@ always_comb begin
     o_data = data;
 end
 
-endmodule
+endmodule

rtl/letc/core/letc_core_cache.sv

@@ -180,8 +180,9 @@ end
 //and then will increment it while it is enabled.
 logic addr_counter_en;
 logic addr_counter_load;
-address_counter #(
-    .ADDR_WIDTH(PADDR_WIDTH)
+counter #(
+    .WIDTH(PADDR_WIDTH),
+    .STEP(4)
 ) address_counter (
     .i_clk(i_clk),
     .i_rst_n(i_rst_n),
@@ -196,16 +197,20 @@ address_counter #(
 //register to drive them. When a word is loaded from memory, we can
 //shift the enable to the left to enable the next word.
 logic sr_rst_n;
-localparam [CACHE_LINE_WORDS-1:0] SR_INIT = 'b1;
+logic sr_load;
+logic [CACHE_LINE_WORDS-1:0] sr_load_data;
+//we will tie off the load data to 1, since we always want to start
+//with the first bit set.
+assign sr_load_data = 'b1;
 shift_register #(
-    .WIDTH(CACHE_LINE_WORDS),
-    .INIT(SR_INIT)
+    .WIDTH(CACHE_LINE_WORDS)
 ) cache_line_wben_shifter (
     .i_clk(i_clk),
-    .i_rst_n(sr_rst_n),
+    .i_rst_n(i_rst_n),
     .i_sdata('0), //if we initialize with 1, only need to shift in 0s
     .i_shift(axi_fsm_limp.ready), //anytime we write a byte, we shift
-    .i_oe('1), //cache sram wen will control writes, so this is unneeded.
+    .i_load(sr_load),
+    .i_ldata(sr_load_data),
     .o_data(cache_line_wben),
     .o_carryout()
 );
@@ -276,28 +281,28 @@ assign axi_fsm_limp.wen_nren = 1'b0;
 assign axi_fsm_limp.size = SIZE_WORD;
 
 /* ------------------------------------------------------------------------------------------------
- * Output Logics
+ * Output Logic
  * --------------------------------------------------------------------------------------------- */
-always_comb begin   
+always_comb begin
     unique case (cache_state_current)
         CACHE_STATE_IDLE: begin
             addr_counter_load  = hit ? 1'b0 : 1'b1;
             addr_counter_en    = 1'b0;
-            sr_rst_n           = 1'b0;
+            sr_load            = 1'b1;
             tag_wen            = 1'b0;
             axi_fsm_limp.valid = 1'b0;
         end
         CACHE_STATE_FILL: begin
             addr_counter_load  = 1'b0;
             addr_counter_en    = axi_fsm_limp.ready;
-            sr_rst_n           = 1'b1;
+            sr_load            = 1'b0;
             tag_wen            = 1'b0;
             axi_fsm_limp.valid = 1'b1;
         end
         CACHE_STATE_WRITE_TAG: begin
             addr_counter_load  = 1'b0;
             addr_counter_en    = 1'b0;
-            sr_rst_n           = 1'b0;
+            sr_load            = 1'b0;
             tag_wen            = 1'b1;
             axi_fsm_limp.valid = 1'b0;
         end

verif/nonuvm/common/shift_register/shift_register_tb.sv

@@ -12,7 +12,7 @@
  * Module Definition
  * --------------------------------------------------------------------------------------------- */
 
-module shift_register_tb();
+module shift_register_tb;
 
 /* ------------------------------------------------------------------------------------------------
  * Parameters
@@ -30,6 +30,8 @@ logic i_rst_n;
 
 logic i_sdata;
 logic i_shift;
+logic i_load;
+logic [SHIFT_REG_WIDTH-1:0] i_ldata;
 
 logic [SHIFT_REG_WIDTH-1:0] o_data;
 logic o_carryout;
@@ -40,8 +42,7 @@ logic o_carryout;
 
 //We insanciate the device under test (DUT), in this case our example_top module, here!
 shift_register #(
-    .WIDTH(SHIFT_REG_WIDTH),
-    .INIT(8'b1)
+    .WIDTH(SHIFT_REG_WIDTH)
 ) dut (
     .*//Hook up all the inputs and outputs to their corresponding signals in the testbench
 );
@@ -70,6 +71,8 @@ default clocking cb @(posedge i_clk);
 
     output i_sdata;
     output i_shift;
+    output i_load;
+    output i_ldata;
 
     input o_data;
     input o_carryout;
@@ -85,6 +88,10 @@ initial begin
     ##1
     cb.i_rst_n <= 1;
     ##1
+    cb.i_ldata <= 'b1;
+    cb.i_load <= 1;
+    ##1
+    cb.i_load <= 0;
     cb.i_shift <= 1;
     ##(SHIFT_REG_WIDTH+2)
     cb.i_shift <= 0;

verif/nonuvm/letc/core/cache/Makefile

@@ -11,7 +11,7 @@
 TBENCH_TOP  := letc_core_cache_tb
 RTL_SOURCES := \
     $(RTL_ROOT)/common/sram/amd_lutram.sv \
-    $(RTL_ROOT)/common/address_counter/address_counter.sv \
+    $(RTL_ROOT)/common/counter/counter.sv \
     $(RTL_ROOT)/common/shift_register/shift_register.sv \
     $(RTL_ROOT)/letc/letc_pkg.sv \
     $(RTL_ROOT)/letc/core/letc_core_pkg.sv \