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ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
Design files and associated documentation for Sonata PCB, part of the Sunburst Project
Side-channel analysis setup for OpenTitan
The user-friendly command line shell.
Split your file into encrypted fragments so that you don't need to remember a passcode
Universal utility for programming FPGA
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenSK is an open-source implementation for security keys written in Rust that supports both FIDO U2F and FIDO2 standards.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Determines the modules declared and instantiated in a SystemVerilog file
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Efficient and minimal collaborative code editor, self-hosted, no database required
Docker images for compiling static Rust binaries using musl-libc and musl-gcc, with static versions of useful C libraries. Supports openssl and diesel crates.
OpenTitan: Open source silicon root of trust
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core