andes: remoteproc: support cacheable remoteproc on SMP systems (#142)

1. The original remoteproc region was marked as non-cacheable.
   However, since the SMP system's L2C (Level 2 Cache) supports coherence,
   the region has been updated to be cacheable.

2. Added a safeguard mechanism to ensure the system enters WFI only
   after PCSm_CTL has been written.

Bugzilla: http://e-andes.andestech.com/bugzilla5/show_bug.cgi?id=35594

Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>

Reviewed-on: https://gitea.andestech.com/RD-SW/opensbi/pulls/142
Reviewed-by: Mina Hui-Min Chou <minachou@andestech.com>
Reviewed-by: randolph <randolph@andestech.com>
Reviewed-by: Tim Shih-Ting OuYang <tim609@andestech.com>

andes: defconfig: add support MPXY for OPTEE

Signed-off-by: Randolph <randolph@andestech.com>

atcsmu: Avoid save/restore HSP CSRs during suspend/resume (#111)

Newer 65 bitmaps remove HSP(Hardware Stack Protection) support,
therefore accessing related CSRs would be an illegal instruction causing the system to hang.

Remove HSP CSRs access to prevent system hang.

Fixes: Bugzilla #30881  [AST v531] ltp/cpuhotplug02 causes system hang on latest 65 bitmap
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-on: https://gitea.andestech.com/RD-SW/opensbi/pulls/111
Reviewed-by: Dylan Dai-Rong Jhong <dylan@andestech.com>
Reviewed-by: Mina Hui-Min Chou <minachou@andestech.com>
Reviewed-by: Peter Yu-Chien Lin <peterlin@andestech.com>

atcsmu: Avoid save/restore HSP CSRs during suspend/resume (#111)

Newer 65 bitmaps remove HSP(Hardware Stack Protection) support,
therefore accessing related CSRs would be an illegal instruction causing the system to hang.

Remove HSP CSRs access to prevent system hang.

Fixes: Bugzilla #30881  [AST v531] ltp/cpuhotplug02 causes system hang on latest 65 bitmap
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-on: https://gitea.andestech.com/RD-SW/opensbi/pulls/111
Reviewed-by: Dylan Dai-Rong Jhong <dylan@andestech.com>
Reviewed-by: Mina Hui-Min Chou <minachou@andestech.com>
Reviewed-by: Peter Yu-Chien Lin <peterlin@andestech.com>

lib: ipi: Rearrange Andes PLICSW to single-bit-per-hart strategy (#87)

Source hart infomation is not necessary in IPI, so we could
use single-bit-per-hart strategy to rearrange PLICSW mapping.

Bit 0 of Interrupt Pending Bits is hardwired to 0.
Therefore, we use bit 1 to send IPI to hart 0,
bit 2 to hart 1, ..., and so on.

Andes AE350 platform is guaranteed to have 31 interrupt sources.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Reviewed-on: https://gitea.andestech.com/RD-SW/opensbi/pulls/87
Reviewed-by: Peter Yu-Chien Lin <peterlin@andestech.com>

OpenSBI v1.4

OpenSBI v1.3

ae350: fix light sleep hang issue

The sbi_printf in light sleep flow seems to
cause an immediate escape from first wfi that
should be executed in opensbi and then enter
the wfi in kernel. Therefore, light sleep hart
will hang in kernel wfi and could not be woken
up.

Fix this by removing the sbi_printf.
Tested in the order of thousands of times.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

OpenSBI v1.2

OpenSBI v1.1