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‎testbenches/project/cn0577_adaq2387x/Makefile‎

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####################################################################################
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####################################################################################
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## Copyright (C) 2025 Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# Makeincludes
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include ../../../scripts/make_tb_path.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_converter.mk
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# Remaining test-bench dependencies except test programs
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_ltc2387
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# list of test programs
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TP := $(notdir $(basename $(wildcard tests/*.sv)))
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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include $(ADI_TB_DIR)/scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=<configuration_name> TST=<test_name> MODE=gui
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#
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# run all test from a configuration
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# make <configuration_name>
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####################################################################################
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####################################################################################

‎testbenches/project/cn0577_adaq2387x/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_16b.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 0
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set ad_project_params(ADC_RES) 16
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set ad_project_params(CN0577_ADAQ2387X_N) 0
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_18b.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 0
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set ad_project_params(ADC_RES) 18
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set ad_project_params(CN0577_ADAQ2387X_N) 0
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_16b.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 1
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set ad_project_params(ADC_RES) 16
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set ad_project_params(CN0577_ADAQ2387X_N) 0
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_18b.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 1
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set ad_project_params(ADC_RES) 18
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set ad_project_params(CN0577_ADAQ2387X_N) 0
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_1lane.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 0
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set ad_project_params(ADC_RES) 18
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set ad_project_params(CN0577_ADAQ2387X_N) 1
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_2lanes.tcl‎

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global ad_project_params
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set ad_project_params(TWOLANES) 1
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set ad_project_params(ADC_RES) 18
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set ad_project_params(CN0577_ADAQ2387X_N) 1
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set ad_project_params(USE_MMCM) 0

‎testbenches/project/cn0577_adaq2387x/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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global ad_project_params
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# system level parameters
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set TWOLANES $ad_project_params(TWOLANES)
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set ADC_RES $ad_project_params(ADC_RES)
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set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N)
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set USE_MMCM $ad_project_params(USE_MMCM)
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#
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# Block design under test
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#
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if {$CN0577_ADAQ2387X_N == 1} {
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source $ad_hdl_dir/projects/cn0577/common/cn0577_bd.tcl
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} else {
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source $ad_hdl_dir/projects/adaq2387x/common/adaq2387x_bd.tcl
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}
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ad_disconnect sys_200m_clk axi_ltc2387/delay_clk
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ad_connect sys_dma_clk axi_ltc2387/delay_clk
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delete_bd_objs [get_bd_nets ref_clk_1]
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if {$CN0577_ADAQ2387X_N == 1} {
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# 120MHz ref_clk for cn0577
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set ref_freq 120000000
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} else {
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# 100Mhz ref_clk for adaq2387x
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set ref_freq 100000000
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}
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ad_ip_instance clk_vip ref_clk_vip [ list \
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INTERFACE_MODE {MASTER} \
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FREQ_HZ $ref_freq \
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]
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adi_sim_add_define "REF_CLK=ref_clk_vip"
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create_bd_port -dir O ref_clk_out
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ad_connect ref_clk_out ref_clk_vip/clk_out
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ad_connect axi_ltc2387/ref_clk ref_clk_vip/clk_out
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ad_connect axi_ltc2387_dma/fifo_wr_clk ref_clk_vip/clk_out
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ad_connect axi_pwm_gen/ext_clk ref_clk_vip/clk_out
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set BA_AXI_LTC2387 0x44A00000
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set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}]
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adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]"
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set BA_DMA 0x44A30000
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set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387_dma}]
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adi_sim_add_define "AXI_LTC2387_DMA_BA=[format "%d" ${BA_DMA}]"
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set BA_PWM 0x44A60000
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set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_pwm_gen}]
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adi_sim_add_define "AXI_PWM_GEN_BA=[format "%d" ${BA_PWM}]"

‎testbenches/project/cn0577_adaq2387x/system_project.tcl‎

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source ../../../scripts/adi_sim.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read common config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Set project params
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global ad_project_params
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# Set to use SmartConnect or AXI Interconnect
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set use_smartconnect 1
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# Create the project
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adi_sim_project_xilinx $project_name "xc7z007sclg400-1"
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source $ad_tb_dir/library/includes/sp_include_dmac.tcl
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source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl
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source $ad_tb_dir/library/includes/sp_include_converter.tcl
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# Add test files to the project
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adi_sim_project_files [list \
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"tests/test_program.sv"
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

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