cn0577_adaq2387x: Partial fix - dco_init generation

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

testbenches/project/cn0577_adaq2387x/system_tb.sv

@@ -39,24 +39,19 @@
 
 module system_tb();
 
-  // reg signals
-
-  reg                     dco_init = 1'b0;
-  reg                     ref_clk_out = 1'b0;
-  reg                     clk_gate = 1'b0;
-  reg                     da_p = 1'b0;
-  reg                     da_n = 1'b0;
-  reg                     db_p = 1'b0;
-  reg                     db_n = 1'b0;
-
-  wire  cnv;
+  wire    ref_clk_out;
+  wire    clk_gate;
+  wire    da_p;
+  wire    da_n;
+  wire    db_p;
+  wire    db_n;
+  wire    cnv;
 
   // test bench variables
 
     `TEST_PROGRAM test(
        .ref_clk_out (ref_clk_out),
        .clk_gate (clk_gate),
-       .dco_in (dco_init),
        .dco_p (dco_p),
        .dco_n (dco_n),
        .da_p (da_p),

testbenches/project/cn0577_adaq2387x/tests/test_program.sv

@@ -52,7 +52,6 @@ localparam NUM_OF_TRANSFERS = 16;
 program test_program (
   input           ref_clk_out,
   input           clk_gate,
-  input           dco_in,
   output          da_n,
   output          da_p,
   output          db_n,
@@ -160,30 +159,31 @@ parameter int num_of_dco = N / 2;
 // dco delay compared to the reference clk
 localparam DCO_DELAY = 12;
 
-reg  dco_init = 1'b0;
+// ---------------------------------------------------------------------------
+// Creating a "gate" through which the data clock can run (and only then)
+// ---------------------------------------------------------------------------
 
-  // ---------------------------------------------------------------------------
-  // Creating a "gate" through which the data clock can run (and only then)
-  // ---------------------------------------------------------------------------
+reg dco_init;
 
- initial begin
+initial begin
+  dco_init = 1'b0;
   forever begin
-    @(posedge clk_gate, negedge clk_gate)
-      if (clk_gate == 1'b1) begin
-        dco_init = ref_clk_out;
-      end else begin
-        dco_init = 1'b0;
-      end
+    @(posedge clk_gate or negedge clk_gate);
+    if (clk_gate)
+      dco_init = ref_clk_out;
+    else
+      dco_init = 1'b0;
   end
 end
 
-  // ---------------------------------------------------------------------------
-  // Data clocks generation
-  // ---------------------------------------------------------------------------
+
+// ---------------------------------------------------------------------------
+// Data clocks generation
+// ---------------------------------------------------------------------------
 
 initial begin
   forever begin
-    @(posedge dco_in, negedge dco_in) begin
+    @(posedge dco_init, negedge dco_init) begin
     dco_p <= #DCO_DELAY  dco_init;
     dco_n <= #DCO_DELAY  ~dco_init;
     end
@@ -213,7 +213,7 @@ assign db_n = r_db_n;
 
 initial begin
   forever begin
-    @ (posedge dco_in, negedge dco_in) begin
+    @ (posedge dco_init, negedge dco_init) begin
       if (`TWOLANES == 1) begin
         r_da_p = data_shift[`ADC_RES - 1];
         r_da_n = ~data_shift[`ADC_RES - 1];
@@ -243,7 +243,7 @@ end
 
 initial begin
   forever begin
-    @(posedge dco_in);
+    @(posedge dco_init);
     if (transfer_status) begin
       if (`ADC_RES == 16) begin
         if (`TWOLANES == 0) begin
@@ -267,7 +267,7 @@ initial begin
         end
       end
     end
-    @(negedge dco_in);
+    @(negedge dco_init);
   end
 end
 

testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg

@@ -43,23 +43,27 @@
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="2,310.252936 us"></ZoomStartTime>
-      <ZoomEndTime time="3,074.252937 us"></ZoomEndTime>
-      <Cursor1Time time="2,610.252936 us"></Cursor1Time>
+      <ZoomStartTime time="0.000000 us"></ZoomStartTime>
+      <ZoomEndTime time="6.608306 us"></ZoomEndTime>
+      <Cursor1Time time="0.000232 us"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
-      <NameColumnWidth column_width="169"></NameColumnWidth>
+      <NameColumnWidth column_width="161"></NameColumnWidth>
       <ValueColumnWidth column_width="66"></ValueColumnWidth>
    </column_width_setting>
-   <WVObjectSize size="22" />
-   <wvobject type="logic" fp_name="/system_tb/test/ref_clk">
-      <obj_property name="ElementShortName">ref_clk</obj_property>
-      <obj_property name="ObjectShortName">ref_clk</obj_property>
-   </wvobject>
+   <WVObjectSize size="23" />
    <wvobject type="logic" fp_name="/system_tb/test_harness/axi_ltc2387/clk_gate">
       <obj_property name="ElementShortName">clk_gate</obj_property>
       <obj_property name="ObjectShortName">clk_gate</obj_property>
    </wvobject>
+   <wvobject type="logic" fp_name="/system_tb/ref_clk_out">
+      <obj_property name="ElementShortName">ref_clk_out</obj_property>
+      <obj_property name="ObjectShortName">ref_clk_out</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/system_tb/test/dco_init">
+      <obj_property name="ElementShortName">dco_init</obj_property>
+      <obj_property name="ObjectShortName">dco_init</obj_property>
+   </wvobject>
    <wvobject type="logic" fp_name="/system_tb/test/dco_in">
       <obj_property name="ElementShortName">dco_in</obj_property>
       <obj_property name="ObjectShortName">dco_in</obj_property>