cn0577_adaq2387x: Generate ref_clk using VIP, update dco generation

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

testbenches/project/cn0577_adaq2387x/system_bd.tcl

@@ -54,6 +54,29 @@ if {$CN0577_ADAQ2387X_N == 1} {
 ad_disconnect  sys_200m_clk  axi_ltc2387/delay_clk
 ad_connect     sys_dma_clk   axi_ltc2387/delay_clk
 
+delete_bd_objs [get_bd_nets ref_clk_1]
+
+if {$CN0577_ADAQ2387X_N == 1} {
+  # 120MHz ref_clk for cn0577
+ set ref_freq 120000000
+} else {
+  # 100Mhz ref_clk for adaq2387x
+ set ref_freq 100000000
+}
+
+ad_ip_instance clk_vip ref_clk_vip [ list \
+  INTERFACE_MODE {MASTER} \
+  FREQ_HZ $ref_freq \
+]
+
+adi_sim_add_define "REF_CLK=ref_clk_vip"
+
+create_bd_port -dir O ref_clk_out
+ad_connect ref_clk_out ref_clk_vip/clk_out
+ad_connect axi_ltc2387/ref_clk ref_clk_vip/clk_out
+ad_connect axi_ltc2387_dma/fifo_wr_clk ref_clk_vip/clk_out
+ad_connect axi_pwm_gen/ext_clk ref_clk_vip/clk_out
+
 set BA_AXI_LTC2387 0x44A00000
 set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}]
 adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]"

testbenches/project/cn0577_adaq2387x/system_tb.sv

@@ -41,12 +41,9 @@ module system_tb();
 
   // reg signals
 
-  reg                     ref_clk = 1'b0;
   reg                     dco_init = 1'b0;
-  reg                     cnv_out = 1'b0;
+  reg                     ref_clk_out = 1'b0;
   reg                     clk_gate = 1'b0;
-  reg                     dco_p;
-  reg                     dco_n;
   reg                     da_p = 1'b0;
   reg                     da_n = 1'b0;
   reg                     db_p = 1'b0;
@@ -56,10 +53,8 @@ module system_tb();
 
   // test bench variables
 
-  always #25 ref_clk = ~ref_clk;
-
     `TEST_PROGRAM test(
-       .ref_clk (ref_clk),
+       .ref_clk_out (ref_clk_out),
        .clk_gate (clk_gate),
        .dco_in (dco_init),
        .dco_p (dco_p),
@@ -71,10 +66,7 @@ module system_tb();
        .cnv (cnv));
 
      test_harness `TH (
-       .ref_clk (ref_clk),
-       .sampling_clk (sampling_clk),
-       .dco_p (dco_p),
-       .dco_n (dco_n),
+       .ref_clk_out (ref_clk_out),
        .cnv (cnv),
        .da_n (da_n),
        .da_p (da_p),

testbenches/project/cn0577_adaq2387x/tests/test_program.sv

@@ -50,7 +50,7 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*;
 localparam NUM_OF_TRANSFERS = 16;
 
 program test_program (
-  input           ref_clk,
+  input           ref_clk_out,
   input           clk_gate,
   input           dco_in,
   output          da_n,
@@ -109,6 +109,9 @@ initial begin
   setLoggerVerbosity(ADI_VERBOSITY_NONE);
 
   base_env.start();
+
+  `TH.`REF_CLK.inst.IF.start_clock();
+
   base_env.sys_reset();
 
   sanity_tests();
@@ -117,6 +120,8 @@ initial begin
 
   base_env.stop();
 
+  `TH.`REF_CLK.inst.IF.stop_clock();
+
   `INFO(("Test Done"), ADI_VERBOSITY_NONE);
   $finish();
 
@@ -163,11 +168,12 @@ reg  dco_init = 1'b0;
 
  initial begin
   forever begin
-    if (clk_gate == 1'b1) begin
-      dco_init = ref_clk;
-    end else begin
-      dco_init = 1'b0;
-    end
+    @(posedge clk_gate, negedge clk_gate)
+      if (clk_gate == 1'b1) begin
+        dco_init = ref_clk_out;
+      end else begin
+        dco_init = 1'b0;
+      end
   end
 end
 
@@ -358,7 +364,7 @@ task data_acquisition_test();
 
     #100ns;
     @(negedge cnv);
-    @(posedge ref_clk);
+    @(posedge ref_clk_out);
     transfer_status = 0;
 
     //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq);