general: Change while(1) calls to forever

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

testbenches/ip/data_offload/environment.sv

@@ -117,7 +117,7 @@ package environment_pkg;
 
     task adc_stream_gen();
 
-      while(1) begin
+      forever begin
         if (adc_src_axis_agent.driver.is_driver_idle) begin
           rx_transaction = adc_src_axis_agent.driver.create_transaction("");
           ADC_TRANSACTION_FAIL: assert(rx_transaction.randomize());

testbenches/ip/data_offload_2/environment.sv

@@ -140,7 +140,7 @@ package environment_pkg;
 
     task adc_stream_gen();
 
-      while(1) begin
+      forever begin
         if (src_axis_agent.driver.is_driver_idle) begin
           rx_transaction = src_axis_agent.driver.create_transaction("");
           TRANSACTION_FAIL: assert(rx_transaction.randomize());

testbenches/project/ad738x/tests/test_program.sv

@@ -249,7 +249,7 @@ end
 
   // Add an arbitrary delay to the echo_sclk signal
   initial begin
-    while(1) begin
+    forever begin
       @(posedge delay_clk) begin
         echo_delay_sclk <= {echo_delay_sclk, m_rx_sclk};
        end
@@ -258,7 +258,7 @@ end
   assign ad738x_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1];
 
 initial begin
-  while(1) begin
+  forever begin
     #0.5   delay_clk = ~delay_clk;
   end
 end
@@ -279,7 +279,7 @@ bit   [31:0]  sdi_preg[$];
 bit   [31:0]  sdi_nreg[$];
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge ad738x_spi_clk);
       m_spi_csn_int_d <= m_spi_csn_int_s;
   end
@@ -297,7 +297,7 @@ assign end_of_word = (CPOL ^ CPHA) ?
                      (spi_sclk_neg_counter == DATA_DLENGTH);
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       spi_sclk_pos_counter <= 8'b0;
@@ -308,7 +308,7 @@ initial begin
 end
 
 initial begin
-  while(1) begin
+  forever begin
     @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       spi_sclk_neg_counter <= 8'b0;
@@ -320,7 +320,7 @@ end
 
 // SDI shift register
 initial begin
-  while(1) begin
+  forever begin
     // synchronization
     if (CPHA ^ CPOL)
       @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
@@ -372,7 +372,7 @@ bit [31:0]  sdi_shiftreg_old;
 assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]};
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge ad738x_echo_sclk);
     sdi_data_store <= {sdi_shiftreg[27:0], 4'b0};
     if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin
@@ -399,7 +399,7 @@ end
 bit [31:0] offload_transfer_cnt;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge shiftreg_sampled && offload_status);
       offload_transfer_cnt <= offload_transfer_cnt + 'h1;
   end

testbenches/project/ad7616/tests/test_program_pi.sv

@@ -137,7 +137,7 @@ bit transfer_status = 0;
 assign rx_db_i = tx_data_buf;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge sys_clk);
     rx_rd_n_tmp <= rx_rd_n;
     fork
@@ -150,7 +150,7 @@ assign rx_rd_n_negedge_s = ~rx_rd_n & rx_rd_n_d;
 assign rx_rd_n_posedge_s = rx_rd_n & ~rx_rd_n_d;
 
 initial begin
-  while(1) begin
+  forever begin
     @(negedge rx_rd_n);
       tx_data_buf <= tx_data_buf + 16'h0808;
       if (transfer_status)
@@ -179,7 +179,7 @@ endtask
 //---------------------------------------------------------------------------
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge rx_rd_n);
   if (transfer_status)
         transfer_cnt <= transfer_cnt + 'h1;

testbenches/project/ad7616/tests/test_program_si.sv

@@ -252,7 +252,7 @@ end
 
   // Add an arbitrary delay to the echo_sclk signal
   initial begin
-    while(1) begin
+    forever begin
       @(posedge delay_clk) begin
         echo_delay_sclk <= {echo_delay_sclk, m_rx_sclk};
        end
@@ -261,7 +261,7 @@ end
   assign ad7616_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1];
 
 initial begin
-  while(1) begin
+  forever begin
     #0.5   delay_clk = ~delay_clk;
   end
 end
@@ -283,7 +283,7 @@ bit   [31:0]  sdi_preg[$];
 bit   [31:0]  sdi_nreg[$];
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge spi_clk);
       m_spi_csn_int_d <= m_spi_csn_int_s;
   end
@@ -299,7 +299,7 @@ assign end_of_word = (CPOL ^ CPHA) ?
                      (rx_sclk_neg_counter == 16);
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       rx_sclk_pos_counter <= 8'b0;
@@ -310,7 +310,7 @@ initial begin
 end
 
 initial begin
-  while(1) begin
+  forever begin
     @(negedge rx_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       rx_sclk_neg_counter <= 8'b0;
@@ -322,7 +322,7 @@ end
 
 // SDI shift register
 initial begin
-  while(1) begin
+  forever begin
     // synchronization
     if (CPHA ^ CPOL)
       @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s);
@@ -371,7 +371,7 @@ bit [31:0]  sdi_fifo_data_store;
 bit [31:0]  sdi_data_store;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge rx_sclk_bfm);
     sdi_data_store <= {sdi_shiftreg[13:0], 2'b00};
     if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin
@@ -399,7 +399,7 @@ end
 bit [31:0] offload_transfer_cnt;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge shiftreg_sampled && offload_status);
       offload_transfer_cnt <= offload_transfer_cnt + 'h1;
   end

testbenches/project/pulsar_adc_pmdz/tests/test_program.sv

@@ -249,7 +249,7 @@ end
 
   // Add an arbitrary delay to the echo_sclk signal
   initial begin
-    while(1) begin
+    forever begin
       @(posedge delay_clk) begin
         echo_delay_sclk <= {echo_delay_sclk, m_spi_sclk};
        end
@@ -258,7 +258,7 @@ end
   assign pulsar_adc_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1];
 
 initial begin
-  while(1) begin
+  forever begin
     #0.5   delay_clk = ~delay_clk;
   end
 end
@@ -279,7 +279,7 @@ bit   [31:0]  sdi_preg[$];
 bit   [31:0]  sdi_nreg[$];
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge pulsar_adc_spi_clk);
       m_spi_csn_int_d <= m_spi_csn_int_s;
   end
@@ -297,7 +297,7 @@ assign end_of_word = (CPOL ^ CPHA) ?
                      (spi_sclk_neg_counter == DATA_DLENGTH);
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       spi_sclk_pos_counter <= 8'b0;
@@ -308,7 +308,7 @@ initial begin
 end
 
 initial begin
-  while(1) begin
+  forever begin
     @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
     if (m_spi_csn_negedge_s) begin
       spi_sclk_neg_counter <= 8'b0;
@@ -320,7 +320,7 @@ end
 
 // SDI shift register
 initial begin
-  while(1) begin
+  forever begin
     // synchronization
     if (CPHA ^ CPOL)
       @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s);
@@ -366,7 +366,7 @@ bit [31:0]  sdi_fifo_data_store;
 bit [DATA_DLENGTH-1:0]  sdi_data_store;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge pulsar_adc_echo_sclk);
     sdi_data_store <= {sdi_shiftreg[27:0], 4'b0};
     if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin
@@ -392,7 +392,7 @@ end
 bit [31:0] offload_transfer_cnt;
 
 initial begin
-  while(1) begin
+  forever begin
     @(posedge shiftreg_sampled && offload_status);
       offload_transfer_cnt <= offload_transfer_cnt + 'h1;
   end