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IstvanZsSzekelyIstvanZsSzekely
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General updates: Updated VIP clocking and reset calls
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
1 parent a5337ee commit a888f41

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29 files changed

+176
-120
lines changed

29 files changed

+176
-120
lines changed

‎testbenches/ip/axi_tdd/tests/test_program.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -569,12 +569,12 @@ program test_program;
569569

570570

571571
task start_clocks();
572-
`TH.`DEVICE_CLK.inst.IF.start_clock;
572+
`TH.`DEVICE_CLK.inst.IF.start_clock();
573573
endtask
574574

575575

576576
task stop_clocks();
577-
`TH.`DEVICE_CLK.inst.IF.stop_clock;
577+
`TH.`DEVICE_CLK.inst.IF.stop_clock();
578578
endtask
579579

580580

‎testbenches/ip/data_offload/tests/test_program.sv‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -127,7 +127,7 @@ module test_program();
127127

128128
setLoggerVerbosity(ADI_VERBOSITY_NONE);
129129

130-
`TH.`PLDDR_RST.inst.IF.assert_reset;
130+
`TH.`PLDDR_RST.inst.IF.assert_reset();
131131
#1;
132132

133133
start_clocks();
@@ -174,33 +174,33 @@ module test_program();
174174

175175
task start_clocks();
176176
#1
177-
`TH.`SRC_CLK.inst.IF.start_clock;
177+
`TH.`SRC_CLK.inst.IF.start_clock();
178178
#1
179-
`TH.`DST_CLK.inst.IF.start_clock;
179+
`TH.`DST_CLK.inst.IF.start_clock();
180180
#1
181-
`TH.`SYS_CLK.inst.IF.start_clock;
181+
`TH.`SYS_CLK.inst.IF.start_clock();
182182
#1
183-
`TH.`PLDDR_CLK.inst.IF.start_clock;
183+
`TH.`PLDDR_CLK.inst.IF.start_clock();
184184
endtask
185185

186186
task stop_clocks();
187-
`TH.`SRC_CLK.inst.IF.stop_clock;
188-
`TH.`DST_CLK.inst.IF.stop_clock;
189-
`TH.`SYS_CLK.inst.IF.stop_clock;
190-
`TH.`PLDDR_CLK.inst.IF.stop_clock;
187+
`TH.`SRC_CLK.inst.IF.stop_clock();
188+
`TH.`DST_CLK.inst.IF.stop_clock();
189+
`TH.`SYS_CLK.inst.IF.stop_clock();
190+
`TH.`PLDDR_CLK.inst.IF.stop_clock();
191191
endtask
192192

193193
task sys_reset();
194-
`TH.`SRC_RST.inst.IF.assert_reset;
195-
`TH.`DST_RST.inst.IF.assert_reset;
196-
`TH.`SYS_RST.inst.IF.assert_reset;
197-
`TH.`PLDDR_RST.inst.IF.assert_reset;
194+
`TH.`SRC_RST.inst.IF.assert_reset();
195+
`TH.`DST_RST.inst.IF.assert_reset();
196+
`TH.`SYS_RST.inst.IF.assert_reset();
197+
`TH.`PLDDR_RST.inst.IF.assert_reset();
198198

199199
#500
200-
`TH.`SRC_RST.inst.IF.deassert_reset;
201-
`TH.`DST_RST.inst.IF.deassert_reset;
202-
`TH.`SYS_RST.inst.IF.deassert_reset;
203-
`TH.`PLDDR_RST.inst.IF.deassert_reset;
200+
`TH.`SRC_RST.inst.IF.deassert_reset();
201+
`TH.`DST_RST.inst.IF.deassert_reset();
202+
`TH.`SYS_RST.inst.IF.deassert_reset();
203+
`TH.`PLDDR_RST.inst.IF.deassert_reset();
204204
endtask
205205

206206
task systemBringUp();

‎testbenches/ip/data_offload_2/tests/test_program.sv‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -152,31 +152,31 @@ module test_program(
152152

153153
task start_clocks();
154154
#1
155-
`TH.`SRC_CLK.inst.IF.start_clock;
155+
`TH.`SRC_CLK.inst.IF.start_clock();
156156
#1
157-
`TH.`DST_CLK.inst.IF.start_clock;
157+
`TH.`DST_CLK.inst.IF.start_clock();
158158
#1
159-
`TH.`SYS_CLK.inst.IF.start_clock;
159+
`TH.`SYS_CLK.inst.IF.start_clock();
160160
#1
161-
`TH.`MEM_CLK.inst.IF.start_clock;
161+
`TH.`MEM_CLK.inst.IF.start_clock();
162162
endtask
163163

164164
task stop_clocks();
165-
`TH.`SRC_CLK.inst.IF.stop_clock;
166-
`TH.`DST_CLK.inst.IF.stop_clock;
167-
`TH.`SYS_CLK.inst.IF.stop_clock;
168-
`TH.`MEM_CLK.inst.IF.stop_clock;
165+
`TH.`SRC_CLK.inst.IF.stop_clock();
166+
`TH.`DST_CLK.inst.IF.stop_clock();
167+
`TH.`SYS_CLK.inst.IF.stop_clock();
168+
`TH.`MEM_CLK.inst.IF.stop_clock();
169169
endtask
170170

171171
task sys_reset();
172-
`TH.`SRC_RST.inst.IF.assert_reset;
173-
`TH.`DST_RST.inst.IF.assert_reset;
174-
`TH.`SYS_RST.inst.IF.assert_reset;
172+
`TH.`SRC_RST.inst.IF.assert_reset();
173+
`TH.`DST_RST.inst.IF.assert_reset();
174+
`TH.`SYS_RST.inst.IF.assert_reset();
175175

176176
#500
177-
`TH.`SRC_RST.inst.IF.deassert_reset;
178-
`TH.`DST_RST.inst.IF.deassert_reset;
179-
`TH.`SYS_RST.inst.IF.deassert_reset;
177+
`TH.`SRC_RST.inst.IF.deassert_reset();
178+
`TH.`DST_RST.inst.IF.deassert_reset();
179+
`TH.`SYS_RST.inst.IF.deassert_reset();
180180
mem_rst_n = 1'b1;
181181
endtask
182182

‎testbenches/ip/data_offload_2/tests/test_program_sync.sv‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -163,28 +163,28 @@ module test_program_sync (
163163

164164
task start_clocks();
165165
#1
166-
`TH.`SRC_CLK.inst.IF.start_clock;
166+
`TH.`SRC_CLK.inst.IF.start_clock();
167167
#1
168-
`TH.`DST_CLK.inst.IF.start_clock;
168+
`TH.`DST_CLK.inst.IF.start_clock();
169169
#1
170-
`TH.`SYS_CLK.inst.IF.start_clock;
170+
`TH.`SYS_CLK.inst.IF.start_clock();
171171
endtask
172172

173173
task stop_clocks();
174-
`TH.`SRC_CLK.inst.IF.stop_clock;
175-
`TH.`DST_CLK.inst.IF.stop_clock;
176-
`TH.`SYS_CLK.inst.IF.stop_clock;
174+
`TH.`SRC_CLK.inst.IF.stop_clock();
175+
`TH.`DST_CLK.inst.IF.stop_clock();
176+
`TH.`SYS_CLK.inst.IF.stop_clock();
177177
endtask
178178

179179
task sys_reset();
180-
`TH.`SRC_RST.inst.IF.assert_reset;
181-
`TH.`DST_RST.inst.IF.assert_reset;
182-
`TH.`SYS_RST.inst.IF.assert_reset;
180+
`TH.`SRC_RST.inst.IF.assert_reset();
181+
`TH.`DST_RST.inst.IF.assert_reset();
182+
`TH.`SYS_RST.inst.IF.assert_reset();
183183

184184
#500
185-
`TH.`SRC_RST.inst.IF.deassert_reset;
186-
`TH.`DST_RST.inst.IF.deassert_reset;
187-
`TH.`SYS_RST.inst.IF.deassert_reset;
185+
`TH.`SRC_RST.inst.IF.deassert_reset();
186+
`TH.`DST_RST.inst.IF.deassert_reset();
187+
`TH.`SYS_RST.inst.IF.deassert_reset();
188188
endtask
189189

190190
task systemBringUp();

‎testbenches/ip/dma_flock/tests/test_program.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -283,15 +283,15 @@ program test_program;
283283
set_dst_clock(100000000);
284284
set_ddr_clock(600000000);
285285

286-
`TH.`SRC_CLK.inst.IF.start_clock;
287-
`TH.`DST_CLK.inst.IF.start_clock;
286+
`TH.`SRC_CLK.inst.IF.start_clock();
287+
`TH.`DST_CLK.inst.IF.start_clock();
288288
#100ns;
289289
endtask
290290

291291
// Stop all clocks
292292
task stop_clocks();
293-
`TH.`SRC_CLK.inst.IF.stop_clock;
294-
`TH.`DST_CLK.inst.IF.stop_clock;
293+
`TH.`SRC_CLK.inst.IF.stop_clock();
294+
`TH.`DST_CLK.inst.IF.stop_clock();
295295
endtask
296296

297297
// Assert external sync for one clock cycle

‎testbenches/ip/dma_flock/tests/test_program_frame_delay.sv‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -159,8 +159,8 @@ program test_program_frame_delay;
159159
`ERROR(("Both DMACs must be set in autorun mode."));
160160
end
161161

162-
stop_clocks();
163162
base_env.stop();
163+
stop_clocks();
164164

165165
`INFO(("Testbench done!"), ADI_VERBOSITY_NONE);
166166
$finish();
@@ -337,15 +337,15 @@ program test_program_frame_delay;
337337
set_dst_clock(100000000);
338338
set_ddr_clock(500000000);
339339

340-
`TH.`SRC_CLK.inst.IF.start_clock;
341-
`TH.`DST_CLK.inst.IF.start_clock;
340+
`TH.`SRC_CLK.inst.IF.start_clock();
341+
`TH.`DST_CLK.inst.IF.start_clock();
342342
#100ns;
343343
endtask
344344

345345
// Stop all clocks
346346
task stop_clocks();
347-
`TH.`SRC_CLK.inst.IF.stop_clock;
348-
`TH.`DST_CLK.inst.IF.stop_clock;
347+
`TH.`SRC_CLK.inst.IF.stop_clock();
348+
`TH.`DST_CLK.inst.IF.stop_clock();
349349
endtask
350350

351351
// Assert external sync for one clock cycle

‎testbenches/ip/dma_loopback/tests/test_program.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -161,11 +161,11 @@ program test_program;
161161
endtask
162162

163163
task start_clocks;
164-
`TH.`DEVICE_CLK.inst.IF.start_clock;
164+
`TH.`DEVICE_CLK.inst.IF.start_clock();
165165
endtask
166166

167167
task stop_clocks;
168-
`TH.`DEVICE_CLK.inst.IF.stop_clock;
168+
`TH.`DEVICE_CLK.inst.IF.stop_clock();
169169
endtask
170170

171171
endprogram

‎testbenches/ip/dma_sg/tests/test_program_1d.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ program test_program_1d;
148148
);
149149

150150
base_env.stop();
151+
`TH.`DEVICE_CLK.inst.IF.stop_clock();
151152

152153
`INFO(("Test bench done!"), ADI_VERBOSITY_NONE);
153154
$finish();

‎testbenches/ip/dma_sg/tests/test_program_2d.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ program test_program_2d;
142142
);
143143

144144
base_env.stop();
145+
`TH.`DEVICE_CLK.inst.IF.stop_clock();
145146

146147
`INFO(("Test bench done!"), ADI_VERBOSITY_NONE);
147148
$finish();

‎testbenches/ip/dma_sg/tests/test_program_tr_queue.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ program test_program_tr_queue;
154154
);
155155

156156
base_env.stop();
157+
`TH.`DEVICE_CLK.inst.IF.stop_clock();
157158

158159
`INFO(("Test bench done!"), ADI_VERBOSITY_NONE);
159160
$finish();

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